Thermal performance of 3DICs

By PHIL GARROU, Contributing Editor

3DICs are assumed to suffer from stronger thermal issues when compared to equivalent implementations in traditional single-die integration technologies. Based on this assumption, heat dissipation is frequently pointed as one of the remaining challenges in the promising 3D integration technology. There are four main aspects differentiating heat dissipation in 3D ICs: chip footprint, die thickness, inter-die interface and TSVs.

Heat dissipation in small hotspots is primarily diffused through the high thermal conductive silicon substrate and spreads in a semi-spherical direction, rapidly decreasing the heat density and lowering the peak temperature. In case of thinned silicon dies in a 3D stack, the inter-die interface layer acts as a thermal barrier due to its poor thermal properties, forcing the heat to spread laterally in the silicon substrate and thus resulting in a temperature distribution which approximates a cylindrical shape.

Thinned silicon dies present reduced lateral heat spreading capacity while poorly conductive adhesive materials used to bond dies together contribute to increase the vertical thermal resistance.
An increase in power density may come from higher power dissipation and/or from a reduction of the
chip footprint. It means either more power needs to be removed from the same package or that the same power dissipation has to go through a reduced chip footprint. While chip footprint reduction is one of the advantages of 3D integration, it usually leads to higher temperatures for the same amount of energy dissi- pation when compared to single-die implementations.

At the 2014 IEEE 3DIC Conference recently in Cork, Ireland, Leti and ST Micro presented two papers on the thermal performance of Packaging 3DICs. Leti shows that inserting TSVs as thermal vias is of limited value. They contend that it is more important to reduce the thermal resistance between the stacked silicon dies which is due to poor thermally conductive layers such as BEOL metallization and underfill.

Thinned dies can present a severe thermal impediment especially to chips with hot spots. Thinned dies present high lateral thermal resistances thus forcing the heat to go through the underfill layer to the next die, which acts as a heat spreader reducing the hotspot temperature. Consequently, the thinner the die the more important is the thermal coupling between dies in case of hotspot heat dissipation.

The use of “thermal TSVs” for thermal mitigation has been routinely reported in the literature. Several thermal-aware physical optimization techniques can be found in the literature which rely on simplistic thermal models where the TSV is treated as a vertical lumped thermal resistor with thermal conductivity calculated according to its diameter and length. Such thermal models ignore the lateral heat transfer and the impact of the thin SiO2 layer, which surrounds each TSV and thermally isolates TSVs from silicon substrate. The poor thermal conductivity properties of the SiO2 dominate the thermal impact of the TSVs in case of hotspot dissipation. Thus while having TSVs in the silicon substrate increases the equivalent vertical thermal conductivity at the same time it causes a lateral thermal blockage effect, especially for fine TSV pitches.

Increasing the TSV density increases the vertical thermal conductivity as well as the lateral thermal blockage effect. Splitting large TSVs into smaller ones increases the ratio of the SiO2 layer thickness to the TSV diameter and hence increases also the lateral thermal blockage effect. Considering TSV technologies with very fine pitch, where this ratio is typically 1:10, also lead to TSV arrays with higher lateral thermal blockage effect.


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