A novel metal gate integration scheme to achieve precise threshold voltage (VT) control for multiple VTs is described.
BY NAOMI YOSHIDA, KEPING HAN, MATTHEW BEACH, XINLIANG LU, RAYMOND HUNG, HAO CHEN, WEI TANG, YU LEI, JING ZHOU, MIAO JIN, KUN XU, ANUP PHATAK, SHIYU SUN, SAJJAD HASSAN, SRINIVAS GANDIKOTA, CHORNG-PING CHANG and ADAM BRAN, Applied Materials, Santa Clara, CA
At very small process geometries, precise control of electrical conductivity is difficult to maintain. The industry requires a viable replacement-gate FinFET architecture to continue scaling high performance CMOS [1, 2] technology and designs. Furthermore, cost-effective and precise VT control to achieve multiple VTs is essential for future ULSI fabrication to achieve optimal power consumption and performance.
In this study, using WFM full fill and combining two techniques — the novel metal composition and ion implantation into the WFM process, we successfully realized three critical aspects for the metal gate for 10 nanometer and beyond. These are: 1) precise effective work function (eWF) control over a 600 millivolt (mV) tuning range to achieve multiple VT, 2) maintaining conductivity for a sub-15 nanometer gate trench, and 3) compatibility to the self-aligned contact (SAC).
A metal oxide semiconductor capacitor (MOSCAP) was used to evaluate the impact of the metal compo- sition and beam line ion implantation on eWF. Ion implantation was performed for some of the samples after high-k dielectric and work function metal deposition on blanket wafers. High frequency capacitance voltage (HFCV) and current voltage (IV) measurements were recorded for the MOSCAP samples. A single damascene structure was used to measure sub-20 nanometer line resistance. A planar MOSFET was also used for evaluating impact on VT and variability.
Work function modulation
FIGURE 1 shows eWF with three compositions of NMOS WF metals (nWFM) compared with RF-PVD titanium aluminum (TiAl) that was used as the nWFM reference metal. Results demon- strated that the difference between the highest and lowest WF was 550 mV and is attributed to the ALD TiAl composition. Nitrogen ion implantation into the ALD TiAl enabled further WF tuning by 100-150 mV steps. This made possible a WF range from near the Si conduction band edge of 4.1 electron volts (eV) for NMOS low VT to above mid-gap 4.7 eV. The WF shift corresponded well to the different dose levels; therefore we demonstrated that ion implantation can be used to pinpoint the target WF. In addition, we found that ion implantation into ALD TiAl does not degrade the gate leakage current and effective oxide thickness (EOT) performance.
Maintaining metal gate conductance for 10nm node
According to the ITRS roadmap, a gate length of 17 nanometers is expected for the 10 nanometer technology node . The problem is that after the high-k cap and etch stop depositions, the gate will have limited space left for the metal fill process . One solution is to fully or mostly fill the trench with WF metal. Using an advanced ALD TiAl deposition process, we were able to fill 13 nanometer wide trenches without any gapfill voids. FIGURE 2 shows the extendible conductance of the ALD TiAl and WF fill process.
It is known that NMOS low WF metals are more prone to oxidization than high WF PMOS films such as titanium nitride (TiN) and that air exposure affects VT control . In our study, degradation on the conductance curves from air exposure was also observed (FIGURE 3). The air exposed sample showed a large offset of the conductance curve to the right while maintaining the slope, i.e. differential resistivity. The TEM (FIGURE 4) shows an additional layer between the TiN barrier and ALD TiAl. Scanning transmission electron microscope- electron energy loss spectroscopy analysis confirmed high oxygen in the white interface. Thus, it is critical to have an in situ ALD TiAl process on the high k TiN cap to maintain conductivity for the 10 nanometer node.
Self-aligned contact compatibility and CMOS VT tuning
At the 22 nanometer technology node, a metal gate SAC is necessary to scale contacted gate pitch . This requires a well-controlled etch back of the metal gate, with subsequent capping of the etch stop material such as silicon nitride (SiN) to prevent contact to gate shorts. Tungsten (W) has been used in volume production because it offers a robust etch back process. In our study, we demonstrated that a controlled recess etch can be achieved with the more conductive TiAl fill compared to W (FIGURE 5). In addition, after metal etch back, a SAC cap was successfully formed with a high density plasma (HDP) SiN fill and chemical mechanical planarization (CMP).
Multiple WF metals need to be integrated for CMOS VT tuning for NMOS and PMOS. In our study we examined the CMOS ALD TiAl flow for four VT tunings. From the results, we propose a new process flow: 1) after the high-k and etch stop layer deposition steps, a fully clustered barrier TiN and nWFM be deposited. Some areas can be masked by photoresist (PR) and the exposed area modified by ion implantation. 2) Etch off the first nWF layer from the PMOS areas. 3) Deposit the second WF (N-3) and barrier. 4) Perform second ion implantation to shift the WF of the third device. 5) Lastly, ALD TiAl is again etched off from the PMOS area WFM (TiN), followed by W or Al fill to fill the remaining gap. The last TiN material serves as the highest WF as well as the barrier layer for W or Al. This flow provides four VTs and metal fill with a clustered nWFM film stack.
Metal WF modulation for VT tuning using a new scheme tunable in the range of 600 mV was successfully demonstrated for 10 nanometer CMOS integration. Ion implantation dose control enabled continuous WF tuning for multiple VT targets. Metal gate conductance data showed the benefit of in situ processing with a TiN barrier and NMOS WF metal. Based on the results, a CMOS flow with NMOS WF-first was proposed for multi-VT tuning.
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