Yield and cost challenges at 16nm and beyond

A new 5D solution utilizes multiple types of metrology systems to identify and control fab-wide sources of pattern variation, with an intelligent analysis system to handle the data being generated.

BY ROBERT CAPPEL and CATHY PERRY-SULLIVAN, KLA-Tencor Corp., Milpitas, CA

In order to produce IC devices at sub-16nm design nodes, semiconductor manufacturers are integrating many novel technologies, including multiple patterning, spacer pitch splitting, 3D logic and memory structures, new materials and complex reticles. The challenges associated with these innovative technologies place huge cost strains on the semiconductor industry. In this environment, high yields and fast ramps play critical roles in helping semiconductor manufacturers maintain profitability.

Process control has helped IC manufacturers accelerate yield over the last 30 years, providing the inspection and metrology technologies necessary for early identification of critical process issues. As IC device design nodes shrunk over time, process control systems kept pace through the implementation of innovative technologies that enabled detection of defects and process variations that inhibited yield and reliability. For example, KLA-Tencor’s optical wafer inspection systems have evolved over the past 30 years from using a tungsten-halogen light source, off-the-shelf microscope objectives and an off-the-shelf sensor to utilizing a laser-pumped broadband light source that is brighter than the sun, optics that are as complex as those used in steppers and custom sensors that are 1,000 times faster than a digital camera. Today’s broadband plasma optical patterned wafer inspectors are now capable of detecting 10nm defects—only four times larger than the diameter of a DNA strand. Moreover, the detection of these defects across all die on a 300mm wafer is equivalent to finding hundreds of coins dispersed across an area the size of the state of California from many miles in space—in an hour.

The multiple technologies used to produce today’s leading-edge devices create challenges for process control. Inspection and metrology systems need to be able to extract signal from smaller defects and process/ pattern variations, often on complex 3D structures with high-aspect ratio features. With novel materials and increased process variability, this signal extraction needs to happen in an environment of increased background noise. In addition, with multiple patterning and more process steps, inspection and metrology tools need to provide increased productivity to enable sufficient production monitoring to detect excursions. For example, FinFETs produced using multiple patterning techniques require process control strategies that utilize advanced inspection and metrology systems that integrate design information and produce the sensitivity necessary to help address smaller critical defects, 3D structures and narrow process windows. In addition, the inspection and metrology solutions must also provide improved productivity to help cost-effectively monitor and control the increased number of process steps associated with fabricating the FinFETs using multiple patterning.

These challenges drive the innovation that produces the unique process control technologies and solutions that find design, patterning or process issues early. This capability is essential for IC manufacturers as it enables production of today’s leading-edge and future technologies with maximum yield and device performance at reduced risk and cost.

The value of process control

The inspection and metrology systems at the core of process control are not used to fabricate IC devices, as they do not add or remove materials or create patterns. However, rather than being superfluous steps in IC manufacturing, process control is critical for making high-yielding, reliable devices. By finding defects and measuring critical parameters, inspection and metrology systems monitor the hundreds of steps required to manufacture a device. These process control measurements help fab engineers identify and troubleshoot process issues when there is an excursion. Process control is fundamentally tied to yield as it would be near impossible for fabs to pinpoint process issues that affect yield without inspection and metrology.

Achieving a fast yield ramp to get products to market quickly is essential for chipmakers—any delay in yield ramp affects revenue [1] and can affect future investment in R&D and the release of next-gener- ation products. By taking steps such as implementing capable process control strategies, a fab can attain shorter development times, faster manufacturing ramps and improved production yield. In fact, the value chipmakers can attain from process control is realized in many forms, including: strong return on investment; lower manufacturing costs and risks; increased revenues; faster time to money; improved cycle times; greater profits; and, business continuity.

In order to provide deeper insight into the value of process control, the ten fundamental truths of process control (FIGURE 1) were compiled. Each of the fundamental truths has been introduced in a series of Process Watch articles [2-10], including details on the applications of these truths to semiconductor IC manufacturing. By understanding the fundamental nature of process control through these ten truths, fabs can implement strategies to identify critical defects, find excursions and reduce sources of variation.

Yield 1

Given the increasing complexity of advanced devices and process integration, one of the most critical fundamental truths that fabs must account for going forward is: Process control requirements increase with each design rule [9]. As FIGURE 2 shows, the number of process steps increases dramatically starting with the 16/14nm design node. As the number of process steps increases, all steps must be held to a higher standard for excursions, defect density and variability. If the per-step yield stays constant at the level achieved for the 28nm node, then the predicted cumulative yield will drop with each smaller design node (FIGURE 3). Because of this compounding nature of yield loss, fabs must obtain tighter controls and lower defect density at each individual process step. This drives the need for new process control strategies that not only detect yield- critical defects and subtle process variations, but also allow engineers to increase inspection and metrology sampling. Such process control capability enables direct monitoring of the increased number of process steps and quick detection of excursions that can have a tremendous impact on wafer manufacturing costs.

Yield 2

FIGURE 3. With increasing process steps, the predicted cumulative yield will drop for advanced design nodes if the per- step yield stays constant at 28nm levels.

FIGURE 3. With increasing process steps, the predicted cumulative yield will drop for advanced design nodes if the per- step yield stays constant at 28nm levels.

 

Strategy for future process control challenges

In moving to sub-16nm design nodes, semiconductor manufacturers are faced with many challenges to Moore’s Law. On the technical side, there are the complexities associated with the integration of novel technologies (e.g., multiple patterning, 3D structures, new materials, complex reticles, increased number of process steps). On the economic side, the convergence of these multiple technologies creates increased pressure on fabs to maintain control of costs. Transistor costs are related to the scaling factor, manufacturing costs and yields. With rising fab, design, development and lithography costs, the best solution semiconductor manufacturers have to achieving the cost goals of Moore’s Law is accelerating yield.

In trying to achieve faster yield ramps, IC manufacturers must confront the many issues surrounding the robustness of their design and process window. On the design side, engineers must be able to find and assess design weak points in order to drive improvements that ensure the device design and fabrication techniques are stable for production. At the sub-16nm design nodes, the required pattern overlay budgets are ≤4.5nm, critical dimension specifications are ~2nm and process windows are extremely narrow. In order to drive the changes necessary to achieve these tight patterning specifications (FIGURE 4), engineers need to understand fab-wide sources of patterning error and the impact of variations on process windows. In this environment of tackling difficult technical challenges within cost targets, process control is essential.

FIGURE 4. For advanced multi-patterning technologies, the sources of patterning errors are fab-wide—occurring both inside and outside the lithography cell. In order to meet the incredibly tight specifications for overlay and critical dimensions, engineers must look at reducing the fab-wide sources of process variation.

FIGURE 4. For advanced multi-patterning technologies, the sources of patterning errors are fab-wide—occurring both inside and outside the lithography cell. In order to meet the incredibly tight specifications for overlay and critical dimensions, engineers must look at reducing the fab-wide sources of process variation.

Developing the necessary process control solutions is challenging—requiring both tremendous innovation and close collaboration among multiple sectors within the semiconductor industry. Not only is it necessary to develop novel technologies that provide advanced inspection and metrology system performance, it is also essential to pursue innovation towards comprehensive process control solutions—strategies that tie process control systems together, so they work in concert in the fab with intelligent analysis systems handling the complex, high-volume data being generated. These process control “system of systems” can help fabs achieve faster yield ramp through quick design verification and process window discovery, expansion and control.

Two examples of process control solutions are shown in FIGURE 5. With defect discovery the goal is to detect and identify yield-critical defects that highlight design issues during development and process drift during production. The discovery system leverages design information through NanoPoint technology on the 2920 Series broadband plasma optical defect inspection systems to find critical pattern defects that affect yield the most dramatically. The Surfscan SP5 unpatterned wafer inspection system aids in preventing yield issues by detecting tiny substrate defects that can distort the subsequent films and pattern structures on advanced 3D devices, such as FinFETs and vertical NAND flash. Finally, the eDR-7110 e-beam review and classification system identifies the defects detected by the 2920 Series and Surfscan inspectors. By producing comprehensive information on critical nanoscale defects, the defect discovery solution helps fab engineers characterize, optimize and monitor their advanced processes to accelerate time-to-market.

FIGURE 5. The future of process control involves “system of systems” solutions which tie together multiple inspection and metrology systems with intelligent data analysis. Shown are two examples of process control solutions: KLA-Tencor’s defect discovery solution on the left and KLA-Tencor’s 5D patterning control solution on the right.

FIGURE 5. The future of process control involves “system of systems” solutions which tie together multiple inspection and metrology systems with intelligent data analysis. Shown are two examples of process control solutions: KLA-Tencor’s defect discovery solution on the left and KLA-Tencor’s 5D patterning control solution on the right.

FIGURE 5. The future of process control involves “system of systems” solutions which tie together multiple inspection and metrology systems with intelligent data analysis. Shown are two examples of process control solutions: KLA-Tencor’s defect discovery solution on the left and KLA-Tencor’s 5D patterning control solution on the right.

The goal of the 5D patterning control solution [11, 12] is to help IC manufacturers obtain optimal patterning on advanced devices. With today’s complex multiple patterning and spacer pitch splitting technologies, patterning errors are no longer tied to the lithography cell. Patterning errors can come from fab-wide sources, such as wafer distortion caused by CMP that directly relates to scanner focus errors. The 5D solution utilizes multiple types of metrology systems to identify and control fab-wide sources of pattern variation, with an intelligent analysis system to handle the data being generated. A critical component of this system solution is the ability to feed back and feed forward metrology data (FIGURE 6). Feedback loops have been utilized for many design nodes. For example, Archer 500LCM overlay metrology systems identify patterning errors and feed back information to the lithography module and scanner to improve the patterning of future lots. But, there is also the opportunity to feed forward information that can further improve patterning. For example the Wafer-Sight PWG patterned wafer geometry measurement system can measure wafer shape after processes such as etch and CMP and this data can be fed forward to the scanner to improve patterning [13 - 15]. Overall, this 5D solution—utilizing fab-wide, comprehensive measurements and an intelligent combination of feedback and feed forward control loops—can help fab engineers expand their process windows, reduce variation within those windows, and ultimately obtain better patterning results.

FIGURE 6. KLA-Tencor’s 5D patterning control solution implements multiple data loops to help optimize patterning. Existing feedback loops (blue) have existed for several design nodes and detect and compensate for process variations. New, optimized feedback loops (green) provide earlier detection of process changes. Innovative feed forward loops (orange) utilize metrology systems to measure variations at the source, then feed that data forward to subsequent process steps.

FIGURE 6. KLA-Tencor’s 5D patterning control solution implements multiple data loops to help optimize patterning. Existing feedback loops (blue) have existed for several design nodes and detect and compensate for process variations. New, optimized feedback loops (green) provide earlier detection of process changes. Innovative feed forward loops (orange) utilize metrology systems to measure variations at the source, then feed that data forward to subsequent process steps.

These comprehensive process control solutions are a critical part of IC industry success, enabling high yields and fast ramps by allowing engineers to more quickly and cost-effectively address a broad range of process issues. Going forward, it is essential to maintain an ecosystem of innovation and collaboration that ensures novel process control systems and solutions are developed that address IC process and cost challenges.

References

1. “The Chip Insider,” VLSI research, March 26, 2013.
2. PriceandSutherland,“Process Watch:You Can’t Fix What You Can’t Find,” Solid State Technology, July 2014. http://electroiq.com/blog/2014/07/process-watch-the-10-fundamental-truths-of-
process-control-for-the-semiconductor-ic-industry/
3. PriceandSutherland,“Process Watch:Sampling Matters,”
Semiconductor Manufacturing and Design, September 2014. http://semimd.com/blog/2014/09/15/process-watch-sampling-matters/
4. PriceandSutherland,“Process Watch:The Most Expensive Defect,” Solid State Technology, December 2014. http:// electroiq.com/blog/2014/12/the-most-expensive-defect/
5. Sutherland and Price, “Process Watch: Fab Managers Don’t Like Surprises,” Solid State Technology, December 2014. http:// electroiq.com/blog/2014/12/process-watch-fab-managers-dont- like-surprises/
6. Sutherland and Price, “Process Watch: Know Your Enemy,” Solid State Technology, March 2015. http://electroiq.com/ blog/2015/03/process-watch-know-your-enemy/
7. SutherlandandPrice,“Process Watch:Time is The Enemy of Profitability,” Solid State Technology, May 2015. http://electroiq.com/blog/2015/05/process-watch-time-is-the-enemy-of-profitability/
8. Price and Sutherland, “Process Watch: The Most Expensive Defect, Part 2,” Solid State Technology, July 2015. http://electroiq.com/blog/2015/07/process-watch-the-most-expensive-defect-part-2/
9. Price and Sutherland, “Process Watch: Increasing Process Steps and the Tyranny of Numbers,” Solid State Technology, July 2015. http://electroiq.com/blog/2015/07/process-watch-increasing-process-steps-and-the-tyranny-of-numbers/
10. Sutherland and Price, “Process Watch: Risky Business,” Solid State Technology, September 2015. http://electroiq.com/blog/2015/09/process-watch-risky-business/
11. Korczynski, “Overlay Metrology Suite for Multiple Patterning,” Semiconductor Manufacturing and Design, August 2014. http://semimd.com/blog/2014/08/26/overlay-metrology-suite-for-multiple-patterning/
12. Moyer, “Feed It Forward (And Back),” Electronic Engineering Journal, September 2014. http://www.eejournal.com/archives/ articles/20140915-klat5d/
13. Lee et al, “Improvement of Depth of Focus Control using Wafer Geometry,” Proc. of SPIE, Vol. 9424, 942428, 2015.
14. Tran et al, “Process Induced Wafer Geometry Impact on Center and Edge Lithography Performance for Sub 2X nm Nodes,” 26th Annual SEMI Advanced Semiconductor Manufacturing Conference, 2015.
15. Morgenfeld et al, “Monitoring process-induced focus errors using high resolution flatness metrology,” 26th Annual SEMI Advanced Semiconductor Manufacturing Conference, 2015.

ROBERT CAPPEL is Senior Director and CATHY PERRY-SULLIVAN is Technical Marketing Manager, Global Customer Organization, KLA-Tencor Corporation Milpitas, CA.

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