Insights From Leading Edge

IFTLE 317 IEEE 3DIC Part 2: 3D Processing at Tohoku Univ & Extreme Thinning Options for Vias Last Pkging

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the IEEE 3DIC Conference.

Tohoku Univ

Koyanagi and co-workers at Tohoku Univ studied the use of Ti as a 3D TSV barrier layer.

Cu was substituted in the early 2000s for Al interconnect wiring which no longer meet the resistivity requirements in the aggressively scaled technology nodes. Cu, which has low electrical resistivity has proved itself as a potential interconnect material, only if necessary barrier layers are in place.

The most serious concern with Cu as interconnect material is the formation of midgap defects in active Si, since it diffuses fast into the Si. Owing to this, the minority carrier life time is reduced several orders even at 200 °C. Moreover during this diffusion process since Cu travels through SiO2, the insulation nature of SiO2 is degraded which can result in premature dielectric breakdown leading to device failure. The well known method to prevent Cu diffusing into SiO2 and then in Si is to sandwich an amorphous metal layer between the Cu and SiO2. Required properties of a good barrier layer are low internal film stress, high thermal stability and low resistivity. Metals with high melting points are known to have larger activation energy for the diffusion to take place.

Although Ta is best suited as a barrier material based on melting point, Ta has more integrated film stress than Ti film, i.e. a 200 nm-thick sputtered Ta film possesses internal stress of 1.4 GPa, whereas the stress in a similar thickness Ti film is 0.8 GPa . Internal stress is the main cause for the delamination of sputtered Ta films. Thus Ti is a better barrier layer based on internal stress.

One way to improve the barrier performance of Ti, is to use a Ti/TiN structure as barrier layer, but TiN has a large resistivity (p~270 µ .

The Tohoku group has found a simple method to improve the barrier ability of Ti layer is to anneal the TSV structures in vacuum at temperatures up to 400 °C. This results in a significant improvement in leakage current characteristics for SiO2 dielectric. TiSix has been identified at the interface between Cu and SiO2 during the sputter deposition.

Another presentation by Tohoku Univ examined the reduction of keep-out-zone in 3DIC by local stress suppression with negative-CTE filler.

The thinning of the IC chips leads to low flexural rigidity of IC chips. In addition, the CTE of the underfill material is larger than that of metal microbumps. In other words, the underfill material shrinks more compared to metal microbumps. IC chips are bent by this shrinkage after the 3D integration process. This CTE mismatch induces local bending stress in thinned Si chips, and in turn effects the MOSFET electrical performance in thinned Si chips.

In general, SiO2 or Al2O3 filler have been introduced into the underfill to reduce the CTE of underfill. High density filler is required to realize a CTE close to the value of the microbumps. However, it is difficult to use the conventional density underfill for 3D IC with fine pitch microbumps due to its high viscosity. What’s required is a low viscosity low CTE underfill.

The Tohoku group suggests a negative CTE material as the filler to suppress the local bending stress. They used manganese nitride-based negative-CTE material as filler. The CTE of this material is -45 ppm/K at the temperature from 65 °C to 100 °C.

Tohoku 1


IMEC & SPTS reported on extreme wafer thinning optimization for via-last applications.

One of the approaches for 3D-SOC W2W bonding is schematically shown below. After oxide bonding, the top wafer can then be thinned and backside via-last TSV contacts can be created to connect electrically to both the top and the bottom wafers.



Two wafer thinning approaches were investigated targeting a 5μm top wafer Si final thickness:

  1. A) A combination of grinding to 25μm followed by an extensive 20μm Si CMP step
  2. B) a combination of grinding to 50μm followed by a short Si CMP step (1μm Si removal) and 44μm Si dry etch process based on a NIR end point detection system performed in an SPTS Rapier XE system.

They conclude that the safest approach combines grinding and a fast Si dry etch which, combined with an in-situ end point detection, enable a very precise and stable etch stop process at the desired

thickness. Moreover, a cost model has shown that this approach is 50% more cost effective as compared to an integration flow that would involve a long and expensive Si CMP step.


For those who havn’t seen it, Amkor has announced that they have completed product qualification of their Silicon Wafer Integrated Fan-Out Technology (SWIFT) WLFO technology for mobile, networking and SiP applications. SWIFT incorporates an “RDL first” process that allows SWIFT wafers to be built and yielded ahead of the assembly process. SWIFT is targeted for production in the second half of 2017 at K5 in Incheon, South Korea.


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