IEDM 2011: Mapping FinFET carrier profiles in 3D

To get a better look at what’s going on inside a FinFET structure, IMEC researchers eschewed the time-consuming process of combining 2D slices, and instead mapped the 3D carrier profiles of FinFETs (2-3nm resolution) using "scanning spreading resistance microscopy" — a progressively shifted gate across multiple identical fins. From that they formed a 3D profile, which allowed them to map electrical resistances and infer charge distribution. It’s a useful technique, they say, to determine how gate underlap, conformality, raised source/drain doping and other issues affect device performance. [Paper #6.1: "3D-Carrier Profiling in FinFETs Using Scanning Spreading Resistance Microscopy"

Next slide: Hollow copper 3D TSVs

Previous slide: FinFETs for sub-20nm SoCs


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won’t automatically be posted to your social media accounts unless you select to share.

Leave a Reply

Your email address will not be published. Required fields are marked *

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <strike> <strong>



New AFM with high definition electrical measurement capabilities
04/16/2015The Nano-Observer, designed by Concept Scientific Instruments, is ideal for current and future AFM research applications….
Thin wafer processing temporary bonding adhesive film for 3D wafer integration
03/24/2015 AI Technology, Inc (AIT) is the first known provider of a film format high temperature temporary bonding adhesive for thi…
Dramatic results achieved in cleaving glass using ultra-short pulsed lasers
03/11/2015ROFIN-SINAR, Inc. introduces the SmartCleave FI laser process and the MPS glass handling system for high speed and precise cl…