Insights From Leading Edge

IFTLE 122: TSMC officially ready for 2.5D, Apple order impact on TSMC

An event that many of us have been waiting for, for a long time finally happened a few weeks ago. At the recent TSMC Open Innovation Platform Ecosystem Forum on October 16th, TSMC announced the foundry reference flow supporting CoWoS (Chip-on-Wafer-on-Substrate) within their open innovation platform (OIP) [link].

The validated CoWoS reference flow enables "multi-die integration to support high bandwidth, low power and achieve fast time–to-market for 3D IC designs." The CoWoS flow allows designers to use existing, mainstream tools from leading EDA vendors. It reportedly allows "a smooth transition to 3D IC with minimal changes in existing methodologies." It includes the management of placement and routing of bumps, pads, interconnections, and C4 bumps; innovative combo-bump structure; accurate extraction and signal integrity analysis of high-speed interconnects between dies; thermal analysis from chip to package to system; and an integrated 3D testing methodology for die-level and stacking-level tests.

TSMC also announced that they have taped out the foundry segment’s first CoWoS test vehicle using JEDEC Wide I/O mobile DRAM interface [link]. This test vehicle demonstrates the integration of a logic SoC chip and DRAM into a single module using the Wide I/O interface. Along with Wide I/O mobile DRAM, the integrated chips provide optimized system performance and a smaller form factor with significantly improved die-to-die connectivity bandwidth. Ecosystem partners included: Wide I/O DRAM from Hynix; Wide I/O mobile DRAM IP from Cadence Design Systems; and EDA tools from Cadence and Mentor Graphics.

EDA systems in place

It seems like only yesterday there were no EDA tools for 2.5/3DIC [ see PFTLE 23, IMEC arrives in Hsinchu and other 3D IC News]. IFTLE is happy to announce that that is no longer the case with several EDA companies including Cadence, Mentor, Synopsys and Ansys were announced by TSMC as partners for their CoWoS reference flow.

[Cliff Hou, VP R&D TSMC, and CP Hsu, VP R&D Cadence]

Cadence announced that TSMC has validated Cadence 3D-IC technology for its CoWoS reference flow with the development of a CoWoS test vehicle that includes an SoC with Cadence Wide I/O memory controller and PHY IP [link]. This is the foundry segment’s first silicon-validated reference flow enabling multiple die integration.

The validated technologies in the 3D-IC solution include: the Cadence Encounter RTL-to-signoff and Virtuoso custom/analog platforms; the Cadence system-in-package products, and recently acquired Sigrity power-aware chip/package/board signal integrity solution that helps

engineers overcome die-stacking and silicon carriers’ challenges from planning through implementation, test, analysis and verification. TSMC’s unique CoWoS combo bump cells, which simplify bump assignment, are now supported automatically in the Cadence Encounter Digital Implementation (EDI) System, QRC Extraction, and Cadence Physical Verification System. The CoWoS Reference Flow is supported with a CoWoS design kit and silicon validation results from a TSMC test vehicle.

Mentor Graphics announced IC physical design, verification, thermal analysis and test design tools that have been selected for TSMC’s new CoWoS (Chip on Wafer on Substrate) Reference Flow [link].

The Olympus-SoC product supports "probe pad routing including micro bump and C4 bump routing, routing between combo bumps, and combo bump stream out in DEF and GDS formats. Inter-die design rule checks (DRC) and layout versus schematic (LVS) checks are performed during layout construction to help ensure rapid signoff."

The Pyxis IC Station custom layout product "provides redistribution layer (RDL) routing and ground plane generation with the ability to do 45 degree angle routes to vias, and specific enhancements for the TSMC flow include improvements to the bump file import process".

The Calibre 3DSTACK sign-off tool verifies physical offset, rotation, and scaling at the die interfaces. It can also trace connectivity and extract interface parasitics to enable multi-die performance simulation. Calibre and FloTHERM 3D computational fluid dynamics software have been integrated to model temperature variation across the CoWoS design.

The Tessent solution enables 3D IC testing. The Tessent test tool " addresses 3D IC multi-die integration challenges including management of placement and routing of micro-bumps, probe-pads, through-silicon-vias (TSVs), and C4 bumps, accurate extraction and signal integrity analysis of high-speed interconnects between dies, thermal analysis from chip to package to system, and integrated 3D testing methodology for die-level and stacking-level tests".

Key features for 3D IC include:

  • Pre-bond testing of TSVs and IOs using contactless wrap;
  • Retargeting of embedded compression scan patterns and built-in self-test (BIST) created at the die level to any die in the stack using DFT access infrastructure;
  • Test generation for shorts or opens between logic die;
  • Test generation for shorts or opens between DRAM and logic die using the memory die’s JEDEC interface;
  • Enhanced memory BIST for thorough testing of vendor independent stacked DRAM die.

Synopsys announced a 3D-IC design solution that is also included in TSMC’s CoWoS reference flow [link]. In support of CoWoS Synopsys has released enhanced versions of its Galaxy Implementation Platform tools for physical implementation, parasitic extraction, physical verification and timing analysis.

TSMC has validated Synopsys’ implementation, analysis and signoff tools, including:

Physical implementation: IC Compiler multi-die physical implementation with support for placement, assignment and routing of microbump, thru-silicon via (TSV), probe-pad and C4; combo bump cells allowing simplified and flexible bump assignment; microbump alignment checks; redistribution layer (RDL) and signal routing, and power mesh creation on CoWoS interconnection layers.

Analysis and signoff: (a) Hercules layout vs. schematic (LVS) connectivity checking between stacked die; (b) StarRC Ultra parasitic extraction support for TSV, microbump, RDL and signal routing metal for CoWoS design interconnection and (c) PrimeTime timing analysis of multi-die systems.

ANSYS and subsidiary Apache announced that their simulation tools were selected for TSMC’s CoWoS reference flow to meet power, noise and reliability requirements and manage thermal run-away, stress and thermal-induced electromigration on 3D-IC structures. RedHawk, Totem, Chip Thermal Model (CTM) , Sentinel-TI ANSYS SIwave and ANSYS Icepak, provide a complete system-level thermal analysis with consideration for chip behavior across CoWoS designs.

TSMC will take over Apple orders from Samsung by 2014

During SEMICON Taiwan last month Gartner predicts TSMC is likely take over all of Apple’s processor contracts (from Samsung) by 2014. Gartner predicted Samsung’s LSI unit will manufacture 700,000 wafers for Apple processors in 2012 with a value of ~ $2.1 B.

Gartner predicts that if Samsung loses all its contracts to TSMC, TSMC would see revenue increases >10% (Gartner estimates TSMC’s 2012 revenues at $16 B).

For all the latest on 3DIC and advanced packaging stay linked to IFTLE……………………………….

(Note the hotel change! Redwood City not Burlingame)


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