At the 2013 IEEE ISSCC researchers from Kobe Univ and the ASET group (Assoc. of Super Advanced Electronic Technologies) presented their work on "A 100 GB/s Wide IO with 4096b TSVs through an active silicon interposer with in place waveform capturing."
As shown in the figure below their work constitutes a major jump in both bandwidth and energy consumption from other published work.
The system design is shown below. The wide IO data bus is capable of 100 GB/s sync bidirectional data transfer at 200 MHz. By putting waveform capture on the active silicon interposer (ASIP), they were able to monitor signal and power integrity within the stack. The silicon interposer provided horizontal and vertical routing for the TSV and microbumps.
Further specifications are given in the chart below.
Asahi Glass enters the Glass Interposer Market
Triton then will apply its proprietary technology to fill the high-aspect-ratio via holes with a copper paste that has the same coefficient of thermal expansion as glass.
At Nvidiaâ€™s annual Graphics Technology Conference last week they announced the Volta, scheduled for release in 2015, will use stacked memories. They see the modules built on 2.5-D interposers since graphics chips generate too much heat to be stacked vertically with memories in a 3D stack.
At the recent IMAPS Device Packaging Conference in Scottsdale, AZ, the big news was that Asahi Glass (AGC) and nMode Solutions had invested $2.1 million to found Triton Micro Technologies to develop glass based 2.5D Interposers. The new company will be headquartered in Tucson AZ with a manufacturing facility planned in CA.
They will manufacture glass interposers using AGC’s EN-A1 alkali-free boro-aluminosilicate glass which has low CTE and thermal expansion properties matched to silicon. EN-A1 reportedly has refractive properties which allow for a low taper when laser drilled, providing for precise pitch control and hole size. EN-A1 has a highly polished surface and can readily accept either thin-film or thick-film metallization directly on the glass without the need for an adhesion layer. Surface roughness of 10 Å or less is typical.
Triton CTO Steve Annas indicated that they are ready for prototyping now.
Nvidia talks GPU + Memory Stacks
In an interview with EE Times [link] Nvidia Chief Scientist Bill Dally reports that the difference between 28 and 20 nm nodes is about 20 to 25 percent "Therefore, process doesnâ€™t matter that much anymore. If Nvidia is clever about architecture and circuit design, then can make up for the fact that Nvidia has competitors [Intel] that are a node ahead." He sees chip stacking as an alternative to moving to the next semiconductor node "at a time when process technology is providing less bang for the buck."
For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…