First things first:
A message from Hannah (9) and Madeline (5):
The 2013 IWLPC Conference was held in San Jose CA this past fall. Lets look at a few of the key packaging papers.
Klaus Ruhmer of Rudolph Technologies addressed the convergence of front end (FE), back end (BE) and flat panel Display technologies that is happening in order to meet the requirements of mid end packaging technologies such as 2.5D on interposer, 3D stacked chips or very thin fan-out packages.
Back-end patterning demand is moving well into the single digit micron range (< 5μm L/S) for current high density applications. One way of reducing cost while achieving such dimensions is to take advantage of economy of scale brought about by larger format processing.
Glass interposers for 2.5D lend themselves to diverge from traditional round wafer form-factors and move to small rectangular panel sizes used early on by the FPD industry. It is thought that processing such panels will require manufacturing techniques which have previously been utilized for Flat Panel Display manufacturing.
A cost analysis by Rudolph concludes that a 1.7X cost reduction in lithography can be achieved by going from a 1X stepper and 300mm glass wafers to a 550 x 650mm glass panel (gen 3 LCD panel) using their panel lithography systems (all other things being equal).
Nanium has been recently involved with establishing 300mm production of FOWLP [see IFTLE 124 “Status and the Future of eWLB; Will Deca lower the cost of FO-WLP?”]
At the IWPC they announced the 300mm scale up of FCI’s (Flip Chip Int) Spheron fan-in WLP technology. They were able to show process capability and reliability on a 500um pitch test vehicle. They are in the process of evolving this to 350u pitch.
We have discussed the Deca adaptive patterning technology previously [see IFTLE 124 “Status and the Future of eWLB; Will Deca lower the cost of FO-WLP?”]
At the IWLPC Boyd Rogers presented the reliability results for a 4X4mm2, 0.4mm pitch 72 IO test vehicle shown below.
They are in the process of doing board level cycling and drop testing.
450mm on Hold??
Several reports including Paul Van Gerven of Bits & Chip and Charile Demergian of Semiaccurate are reporting that ASML has stopped 450mm litho development.
Van Gerven reports that customers Intel, Samsung and TSMC do not appear to be on the same page moving forward. Demergian reports that he has heard that Intel “…was delaying 450mm production by a considerable amount.”
Starting in July, ASML minority equity investments by its largest customers. Intel was the first acquiring 15% equity ownership. Part of the deal was a contractual commitment from Intel for advance purchase orders for 450 mm and EUV development and production tools. In August, TSMC took a 5% stake in ASML ( $1.04 B) and TSMC committed $341 million to ASML’s R&D programs.
While it has been widely reported that volume production at 450-millimeter was scheduled to start in 2018 at the 10nm node, these recent announcements could indicate that this 2018 start date might be optimistic.
For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…
I like the Dutch sentence you mixed into the content. Courtesy of ASML I assume ?
Keep the 450mm updates coming.