Letâ€™s take a look at some of the key presentations from the SEMI Summit that took place in January in Grenoble.
Gartner â€“ 3D Market Forecast
Stromberg of Gartner gave a market forecast of greater than 1.5M 300mm wafer equiv per month or 2B units / year of 2.5/3D (non MEMS non CIS) by 2018 but then listed several pages worth of technical issues that could affect the forecast.
In emerging technologies like 2.5/3DÂ guaging market timing and size is an art, not a science but Iâ€™m not sure what numbers like this are worth if you preface them by saying they could be inmpacted by thermal issues, yield issues, design issues andÂ competitive treats by PoP andÂ WB devices. Of course all those things are true, but then what kind of confidence do we have in the nubmbers / timing ?Â This is true for al lthe marketing houses not just Gartner.
GF has been detailing their imminent commercialization of 2.5/3D IC for several years. Their current status report is shown below.
Their response to Interposer TSV formation, front side routing and backside reveal and RDLÂ issues are shown below. High IO counts require dense interposer frontside routing (i.e. over 1600 wires for a HBM port.
The GF supply chain for 2.5D productization is shown below:
Miekei Leong , VP TSMC, gave the standard TSMC CoWoS pitch but did offer a definition of their supply chain model where OSATS are now integrated as part of the supply chain.
Another interesting roadmap showed TSMC demonstrating HBM (high bandwidth memory) on CoWoS by 4Q 2014.
IMEC â€“ Cost Analysis
Eric Beyne of IMEC presented data on a cost breakdown of their 5 x 50Âµm TSV full flow 3DIC process (without stacking) showing the TSV middle fabrication process and the thin and backside eveal processing are about equivalent in cost.
They find that a lot of cost is invested in CMP processing which can be improved by reducing the Cu overburden after TSV fill.
This can be compared to the 10 x 100Âµm TSV costs presented by Ramaswami of Applied Materials shown below:
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