Insights From Leading Edge

IFTLE 188 IMAPS Device Packaging Conf Part 2: AMD, SCP

Continuing our look at the recent IMAPS DPC with several key presentations.


AMD’s keynote presentation by Bryan Black updated us on their thoughts about “Die Stacking and High Bandwidth Memory.” Black stated that “…while die stacking is catching on in FPGAs, Power Devices, and MEMs, there is nothing in mainstream computing CPUs, GPUs, and APUs …HBM Stacked DRAM will change this!”

As we have discussed on IFTLE many times, Black agrees that future nodes will NO LONGER bring down transistor costs which has been a longstanding premise of Moore’s Law.


Die Stacking Motivation

  • Process complexity is increasing and yield is dropping as mask count increases
  • Large die sizes will continue to have yield challenges


Black adds that die partitioning is challenging and there is significant microarchitectural research to be done since the buss to connect partitioned chips is very complex.

As we heard from Hynix at the RTI ASIP conference in December 2013 [see “AMD and Hynix announce joint development of HBM memory stacks,” the first generation of Hynix high bandwidth memory is now sampling.]


This results in a 3X improvement in bandwidth per Watt.


Black envisions silicon interposers replacing SoC for high end platforms in the future.


Black announced that AMD AND Hynix were looking for partners to begin immediate development of such products.


In an attempt to expand the usage of their eWLB technology, SCP announced FlexLineTM as a “breakthrough manufacturing method for Wafer level packaging”.

Tom Strothmann of SCP pointed out that OSATS have traditionally been forced to use wafer processing equipment sets for both 200 and 300mm wafers, that typically have higher cost and capability than needed.

Currently, separate equipment sets are required to manufacture WLCSP from 200 or 300mm wafers whereas the FlexLine process allows them to be manufactured on the same equipment set.

The SCP FlexLine process flow is based on the SCP commercial eWLB FO-WLP process [ see IFTLE 124, “Status and the Future of eWLB…”]. Single and multi die fan-out package solutions have been in HVM since 2009 with more than 500MM units shipped. SCP eWLB have passed all standard component and board level reliability tests.

FlexLine uses eWLB technology to dice and reconstitute incoming wafers of various sizes to a standard size, which results in wafer level packaging equipment becoming independent of incoming silicon wafer size.

fig 2 SCP

The following 2D/2.5D products can be fabricated on the same FlexLine using a  standard process flow.

fig 3 SCP

Process Flow:

– Dice the wafer to dimensions slightly larger than nominal die size

– Process through reconstitution, redistribution and ball drop

– singulate removing the mold compound from the side of the die and reducing the die size back to the nominal size

To create an encapsulated WLCSP (eWLCSP):

– Dice the wafer at nominal die size

– Process through reconstitution, redistribution and ball drop

-Final singulation is done larger than the die size, leaving a protective layer of mold compound on the sides of the die

– The end product here  is a e-WLCSP that cannot be made with conventional WLCSP processes

Strothmann indicates that SCP COO studies conclude that the added cost of reconstitution is offset by the larger panel size that is processed. CTO BJ Han adds “…with FlexLine we are able to help our customers achieve at least a 15-30% cost reduction using the optimum design requirements for their WLCSP devices.”

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…



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