By Dr. Phil Garrou, Contributing Editor
The Latest on IBM and GF
Craig Wolf of theÂ Poughkeepsie Journal reports confirmation from Global Foundries that 150 to 200 IBMâ€™ers will move from IBMâ€™s East Fishkill chip plant to GlobalFoundriesâ€™ plant in upstate Saratoga County. GF has confirmed a contract with IBM in which â€śtechnical workersâ€ť based at the East Fishkill will work for eight months at GFâ€™s Fab8 chip plant. IBM refused comment on the deal.
While one cannot conclude that his confirms the imminent sale of the IBM Semiconductor division to GF (which IFTLE has predicted for several years) , it certainly indicates that things are slow in the IBM plant.
Continuing our look at the recent 2.5/3DIC Forum at SEMI Singapore.
Naniumâ€™s presentation â€śWafer Level Fan-Out as Fine-Pitch Interposerâ€ť focused on the premise that FO-WLP technology, eWLB, has closed the gap caused by the delay in the introduction of Si or glass interposers as mainstream high volume commodity technology and that eWLB offers an alternative with sufficient capability for many applications in high volume at reasonable cost.
PoP structures such as those shown below are being readied for portable applications where less than 1mm thickness is required.
Nanium is working with AT&S to develop technology for reconstitution in laminate vs traditional eWLB which forms a wafer out of molding compound.
Fujitsu presented on â€śHighly reliable chip to chip Cu wiring technologies for 3D/2.5D interconnection.â€ť Their premise is that as interconnect gets finer and finer traces will need full barrier layer protection similar to what is done on chip with dual damascene, especially when the interposer is a high density PCB. This is shown by HAST failures as shown below.
Their proposed failure mechanism is:
– Halide ions and organic acid accumulate around the anode Cu
– Anode Cu dissolves and Cu ions are formed
– Cu ions diffuse and drift into insulating materials
– Cu dendrite growth on cathode surface triggers dielectric breakdown
A barrier layer is needed to prevent Cu corrosion. SiN failure is due to cracking due to the CTE mismatch.
Thorsten Matthias reviewed EVG solutions for interposer manufacturing.
Of special interest was his review of the work of GaTech and Zeon looking at the insulation of interposer TSVs with polymers instead of oxide. Oxide liner is usually less than 1ÎĽm thickness and the cost scales with thickness whereas polymer liners can be much thicker and the cost is independent of thickness. The GaTech simulations show the polymer liners will give superior electrical performance. FEA shows the polymer liners should show a Reduction of thermal induced mechanical stress.
EVG proposes spray coating as the technique to get the TSV insulated with polymer as shown below. EVG wafers were processed on an EVG NanoSpray coater with JSR Micro WPR 5100 positive resist and BCB for polymer insulation.
IFTLE notes that cross sections were shown for 40um dia TSV but not for the more common 10 x 100um TSV.
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The main issue for mass adoption of TSVs is still the high cost.
Recently, there have been news about using titanium as an in-between layer between the wafer and the Cu filling, but this look just a modest step toward affordable TSVs for most applications.
I guess unless some company comes out with a radical innovation 3D ICs would remain too expensive to be used in most applications