By Dr. Phil Garrou, Contributing Editor
We are a bit out of chronological sequence, but as usual the ECTC was chuck full of materials worthy of coverage. Since the presentation is in six parallel sessions it takes time to go back and read all of them, and, since the papers are published in IEEE Explore, I do not have the power point presentations to summarize for you.
Let’s start off with some papers concerned with warpage issues.
As we continue to miniaturize, warpage remains the main problem encountered in all areas of advanced packaging. Kotake of Hitachi Chemical addressed “Ultra low CTE core materials for next generation thin CSPs” They describe ultra low CTE (1.8) core materials (E-770G) which are used to reduce warpage in PoP packages. Hitachi simulations show that the CTE of core materials has more impact that the modulus.
Best results are obtained when using the new material E-770G for both core and prepreg.
Kim and co-workers at Amkor reported on “Strip grinding Introduction for thin PoP.” Typical PoP used in mobile products consists of a logic function In the bottom package and a memory function in the top package. The most difficult barrier to fabricate the thin PoP is warpage control. Amkor TMV (through mold via) PoP structures can be overmolded or exposed die (to allow for heat sinking). When trying to thin the package, there is a limit to the thinness of the overmold and a limit to the silicon die thickness since thinner die result in die chipping or cracking during handling. In the thin mold cap case, it’s not easy to control the package warpage. The warpage can be controlled with a thicker substrate, but this increases the package thickness.
The concept of strip grinding is to grind the mold compound and die together. The advantage of strip grinding is to use normal die thickness and mold cap thickness, thus reducing the risk of thin die handling and narrow mold clearance. Mold flash is eliminated through the grinding methodology. By applying a strip grinding process, we can easily generate a very thin die and mold cap.
Double side molded structures are possible, which help make a balanced structure on top and bottom which tends to improve the warpage performance. Bottom side mold is difficult, because the BGA ball is mounted on the bottom area.
For the double-sided mold process flow, chip attach on the top side and BGA ball attach on the bottom side need to be done first followed by double side mold. The bottom molding is ground until the bottom ball is exposed. To remake a BGA, a second ball attach needs to be performed to generate a proper BGA standoff.
Warpage simulations were done for a variety of die/substrate/mold thicknesses, as shown below.
Warpage is minimized when (a) thin die is double-side molded, i.e leg 6; (b) very thin die i.e leg 3 or (c) thick substrate to balance mold, i.e leg 1.
Bchir of Qualcomm discussed “improvement of substrate and package warpage by copper plating optimization.”
While substrate warpage is typically approached through modification of dielectric material properties (such as CTE, Tg, modulus), layer thicknesses (core, prepreg, solder resist and Cu thickness), and Cu areal density per layer there is also an impact from the Cu plating process. Electroplated Cu thin films have porous grain boundaries, wherein grain boundary volume is strongly dependent on electroplating conditions and subsequent thermal processing. During thermal processing, Cu grains grow and merge, eliminating grain boundaries and causing shrinkage. The residual stress in the initial deposit, coupled with shrinkage during subsequent thermal processing, strongly impacts the warpage of the substrate and package. This is compounded by the inherent front-to-back Cu density imbalance which is typical in substrate design.
Choice of electrolytic Cu plating solution has significant impact on the magnitude of package warpage. The influence of Cu plating solution on warpage is related to the resulting grain size distribution and stress state deposited from a given chemistry. Plating additives can be co-deposited as impurities into the Cu layer, and have been shown to strongly impact residual stress and grain coarsening behavior of the Cu deposit.
They found that reducing the plating current density for a given plating solution led to substantial reduction in package warpage. Also, an increase in the plating current density causes a reduction in the deposited grain size, hence a reduction in current density would lead to larger deposited grains and thus larger grains would mean reduced grain boundary volume, less “shrink” in the Cu layer and lower residual stress in the Cu.
Eric Beyne’s group at IMEC detailed their work on “Minimizing Interposer Warpage by Process Control and Design Optimization.” Imec’s silicon interposer technology consists of 10×100μm TSV, four thick damascene BEOL layers, Cu bumps and redistribution layers (RDL) front side and back side.
They calculated and measured 300mm wafer bowing at different stages of interposer BEOL processing, as shown below. There is good agreement between simulation and measurement. For a 10mm x 20mm interposer, bowing is measured as 30um (short side) x 130um.
Bowing mitagation was investigated by:
– Replacing standard Pre-Metal-Dielectric (PMD) layer by a thicker and more compressive insulator
– The use of thinner Metal1 and Metal2
– The use of a more compressive oxide in the BEOL
– Replacing the standard PMD layer (300 nm/80 nm SiO/SiC layer) by a thick PECVD oxide with -170 MPa compressive results in a bow reduction of around 150 um (-37% bowing).
At die level, bowing value of around 45 μm (-59% bowing) is predicted by the model for a 20 x 20mm interposer.
The use of thinner Metal1 and Metal2 will increase the sheet resistance of the two layers and consequently may impact the electrical performances of the interposer. The figure below shows that reducing the thickness of M1 and M2 effectively reduce the bowing and that a thickness of around 0.4μm could be a good trade-off between bowing and performance decreases.
Small modification of the stress of the oxide can be very efficient to decrease the bowing at wafer but also thin die level.
They conclude that “the use of a more compressive and thicker PMD insulator layer, a reduction in Metal1/Metal2 thickness, the use of more compressive oxide within the BEOL, are promising and easy to implement solutions to reduce interposer bowing with a limited impact onto its performances.”
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