By Dr. Phil Garrou, Contributing Editor
Continuing our look at the 2014 IMAPS Conference held in San Diegoâ€¦
Shorey of Corning Glass gave an update on glass panel fabrication. He noted that â€śthere are challenges in applying standard plating processes to glass,” but Autotech has recently reported significant progress in the ability to metallize glass vias using new adhesion promoters. They show complete fill with little overburden in 80um holes in 300um glass.
They also showed 370 x 470 x 0.3mm glass panels. A Rudolph Jetstep S3500 was used to create â€ś~3um L/Sâ€¦with additional work we fully expect to be able to resolve < 3um L/Sâ€ť. Â Smallest vias shown were 35um in 100um glass.
In an aligned presentation, Ruhmer of Rudolph discussed high resolution patterning to enable panel based advanced packaging.
When examining litho steps for panel processing Rudolph points to the following key items: minimum resolution, overlay accuracy, sidewall angle and CD control, depth of focus (DoF), exposure field size and warped panel handling capability.
– optical characteristics of suitable litho systems should offer N/A of 0.1 to 0.15 in order to meet L/S resolution requirements for high density interposers (1-2um)
– depending on the complexity of the interposer 5 or more mask layers per side can be required. In general the overlay accuracy should be ~ 1/3 the resolution limit of the system, so for a resolution of 1.5um the overlay accuracy should be 0.5um. Reconstituted substrates for FO-WLP is more complex due to die shift.
– accurate focus control across the wafer is required for tight CD control and consistent sidewall angle in photo dielectrics
– depth of focus for back end processing requires 10um or greater range, not typically available in front end steppers.
– exposure field size should at least cover one die to avoid stiching.
– in initial panel based FO-WLP testing warpage of approx 10mm was observed for a Gen 2 glass panel. Equipment withÂ warped handling features like switchable and compliant gaskets on chucks and handlers ae needed for litho and other processing steps.
Corning / Unimicron / Qualcomm
Corning, Unimicron and Qualcomm reported on their low cost interposer development program.
They sought to show feasibility of interposer manufacturing on their 200um thick 508 x 508mm glass panel format. Daisy chains are connected with 100um TGV (through glass vias) and 8/8 L/S.
The process flow using ABF dielectric is shown below.
Early handling led to glass breakage. The ABF lamination (Ajinomoto) gave the thin glass panel mechanical support more handlable.Â Then vias were created through the ABF.
Warpage of the glass panels were compared to laminate (BT) panels of the same size with 200um core thickness. The glass panels showed 3X lass warpage.
DNP reported on a comparison of fabrication processes and electrical performance of silicon and glass interposers. I should note that these appear to be DNP processes, not necessarily standard processes. For instance they comment that silicon is fabricated on 200mm lines but glass can be fabricated on large panel lines. The facts actually are that Si is fabricated commercially on 300mm lines and large panel glass interposers are in R&D stage.
Their silicon and glass processes ae compared below.
In the silicon process, the holes are formed by ICP-RIE. The wafer is then thermally oxidized and coated with PECVD SiN. The holes are seed sputtered then plated with Cu, CMPâ€™ed and both sides covered with Cu/PI RDL. TSV are on 200um pitch.
In the glass process, 50um TSV on 200um pitch are formed in 0.3mm glass by focused electrical discharge (Recall AGC is a proponent of this method). After Ti/Cu seed the vias a electroplated with copper and the surfaces CMPâ€™ed. Copper / PI RDL are added to both sides.
Glass interposers showed better high freq. performance than silicon as was expected.
Mori of Shinko described their development of Glass Interposers with fine pitch ubumps and their warpage results. They examined glasses with CTEâ€™s of 3.2 and 9.5 ppm and corresponding moduli of 73 and 90 GPa. Their design rules are shown below.
Three laminates were examined with properties shown in the table below:
Warpage of the die on interposer on substrate showed that warpage of the assembled stack is lowered with lower CTE laminate substrate but is not affected by the CTE of the glass Interposer. Modeling verified these results.
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