Insights From Leading Edge

IFTLE 230 SEMI 3D Summit – Grenoble: Oerlikon, ST Micro, Qualcomm

By Dr. Phil Garrou, Contributing Editor

In the next two weeks, we’ll take a look at some of the more interesting presentations from the SEMI 3DIC Summit in Grenoble last month.

Oerlikon – Capabilities of Highly Ionized Sputtering (HIS)

Juergen Weichart of Oerlikon Systems discussed the capabilities of highly ionized sputtering.

It has been known for many years that filling of high AR TSV required ionized plasmas as shown below.

Oerlikon 1


Cross sectional analysis shows that HIS which deposits 462um of Ti adhesion/barrier layer on the Si top surface and 17um in the bottom of the TSV only results in a 10-12nm coating on the TSV sidewalls.

oerlikon 2


Deposition rates, step coverage deposit resistivity and stress for both TSV and RDL processes are compared in the table below.

oerlikon 3


ST Micro – Interposers for Networking ASICS

Georg Kimmich of ST Micro gave a presentation on Network packaging trends.

Below we see the current typical packaging for a networking ASIC chip

ST 1


Higher I/O density and memory bandwidth, required for future Networking ASIC chips, can be handled by use of 2.5D packaging with high density interposers. Both Hynix high bandwidth memory (HBM) and Micron Hybrid  memory cube (HMC) memories are suitable for such networking applications.

Memory can be inserted into the packages with the following silicon and laminate interposer options.

ST 2


While the Hybrid Organic Substrate solutions (2.1D) are the most promising in terms of cost and supply chain simplicity technologically they are less advanced.

They conclude that the very high cost of ASIC, HBM and high density interposers results in very high pressure to achieve high assembly yield. The supply chain for HBM integration are ready for prototyping now and volume production in the H2 2016 time frame.

Qualcomm – Partitioning of Large Die

Mustafa Badaroglu of Qualcomm addressed the topic of “2.5 and 3D Integration: Where we have been, where we are now and where we need to go with much the same presentation that Riko Radojcic gave at the Ga Tech Interposer Workshop in November.

They conclude that large dies can be economically partitioned into smaller dies and repackaged with several options including (1) low cost SI interposer with no substrate, (2) fan out WLP or (high density organic interposer as shown below.

qualcomm 1


  • Split die requirement: 2um L/S between die

Required to support ~ 2000D2D connections

  • PoP memory requirement: PoP via + RDL

Required to leverage standard PoP package

  • Si form factor : two ~12mm x ~6mm die
  • Electrical Requirement: 3LM interconnect

Required for signal, PoP and PDN/SI needs

  • Package = 15mm x 15mm x <1mm

Required to meet the usual SP constraints

  • Cost requirement < 1c/mm2 in HVM


SoC large die partitioning challenges

–What function goes on which die

–Balance of die areas

–Power-performance trade offs


For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…


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