Insights From Leading Edge

IFTLE 242 Advanced Packaging at the ConFab

By Dr. Phil Garrou, Contributing Editor

At the recent ConFab meeting in Las Vegas, aside from all the talk about consolidation (see IFTLE 241), Bill Chen from ASE and Li Li from Cisco put together a great Advanced Packaging session.

(L to r) Bill Chen (ASE), Ram Viswanath (Intel), Kevin Tran (Hynix), CP Hung (ASE), John Knickerbocker (IBM) and Li Li (Cisco)

(L to r) Bill Chen (ASE), Ram Viswanath (Intel), Kevin Tran (Hynix), CP Hung (ASE), John Knickerbocker (IBM) and Li Li (Cisco)

CP Hung, VP of R&D for ASE discussed “Integrating 3D IC into the IC Packaging DNA” Hung proposed that 2.5D IC significantly extends FCBGA technology as shown in the fig below.

Fig 2


Kevin Tran of Hynix announced that HBM (high bandwidth memory) has completed the qualification for mass production in March 2015. Each application has different memory requirements, but most common are high bandwidth and density. He indicated that packaging technology has become a key enabler for high performance, small form factor, low cost memory solutions.

Fig 3


Hynix is readying HBM 2 which will be applied for HPC, graphics, servers and network computing. High end graphics products have already been announced like Pascal at Nvidia and Greenland at AMD. Can Intel be far behind? IFTLE thinks not.

Fig 4


Ram Viswanath of Intel pointed out that “…the ability to monolithically integrate diverse functionality on the die has become impractical due to technology complexity and affordability” and that “on package integration is playing a key role in bringing diverse functionality into smaller form factor.” Key focus is on delivering

– performance for servers

– form factor for wearable products

– cost/form factor for client products

-low cost for future IoT products

Intel’s evolution of dense interconnect is shown below. The Xenon Phi for HPC uses memory stacks on an interposer (reportedly Micron HMC).

Fig 5


Intel compares  side-by-side multichip packaging to 2.5D interposers to 3D stacking in the table below. (note – IFTLE cannot support some of the conclusions on EMIB without seeing the actual data first).


Multichip                  side-by-side

2.5D Interposers

3D stack

Si interposer


IO/mm/layer 30-50 180-250 180-250 NA
IO/mm2 85-120 330-625 330 625
Elect perform (IO)        
Elect Perform (Power)        
Perform (Watt)        
Manuf complex (Yield)        
Thermal limits        

*2.5D designs are comparable

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won’t automatically be posted to your social media accounts unless you select to share.

One thought on “IFTLE 242 Advanced Packaging at the ConFab

Leave a Reply

Your email address will not be published. Required fields are marked *