ByÂ Dr. Phil Garrou, Contributing Editor
Over the next few weeks of the summer, I will be covering as much of the 65th IEEE ECTC as I can. They call themselves the â€śPremier International Packaging Conferenceâ€ť and they are. Authors from companies, research institutions, and universities from over 25 countries presented their work at ECTC, illustrating the conferenceâ€™s global focus. In addition, the ECTC offered 16 Professional Development Courses (PDCs) and Technology Exhibits.
This year there were 350 papers presented in 36 oral sessions covering 3D and TSV technologies, wafer level packaging, electrical and mechanical modeling, RF packaging, system design, and optical interconnects.
This years conference leaders include (from L to R) Sam Karikalin, Broadcom, Beth Kesser, Qualcomm, Alan Huffman, RTI Int and Henning Braunisch, Intel.
First, letâ€™s look at some advances in thermos-compression bonding.
Jie Fu of Qualcomm discussed â€śThermal Compression Bonding for Fine Pitch Solder Interconnectsâ€ť. Mass reflow-based interconnects, using either solder bump or Cu-column on bond on lead are the typical low-cost flip chip assembly approachs used by industry. These interconnects face challenges related to shorting and non-wets at sub 100um pitches. Transitioning below 100um pitch requires a new approach, such as thermos-compression flip chip (TCFC). While TCFC provides higher accuracy bonding and allows for use of smaller solder cap which enables tighter FC pitch, it also presents new challenges. The major challenges for TCFC bonding include lower throughput and control of non conductive paste (NCP) voids. Overall, bond head ramp rate, temperature uniformity, peak temperature and dwell time must be fine tuned in tandem to compensate for manufacturing tolerances and to get the desired end of line solder joint structure. In addition, controlling the temp exposure for the NCP material before NCP cure is critical to enable a robust TCFC solder joint. To much thermal exposure and the NCP begins to cure prior to solder melting, which can leading to NCP entrapment and unreliable TCFC solder joints. Laminate surface finish is also an important variable.
In a similar study Cho and co-workers at GlobalFoundries presented â€śChip Package Interaction Analysis for 20-nm Technology with Thermo-Compression Bonding with Non-Conductive Pasteâ€ť. Strong market demand for finer pitch interconnects to enable higher I/O counts in a smaller form factor is driving another transition from conventional MR bonding process to thermo-compression bonding using non-conductive paste (TC-NCP). FEA simulation results for TC-NCP vs mass reflow show that TCNCP has significantly reduced thermo-mechanical stress at the ULK level and the bump level.
Horst Clauberg of K&S discussed â€śHigh Productivity Thermocompression Flip Chip Bondingâ€ť. There is tremendous effort by IDMs, OSATs, materials suppliers and equipment suppliers to bring thermos-compression bonding to commercial reality. The most significant technical challenges have for the most part been solved and limited commercial production is taking place. However, relatively low throughput and high equipment cost create adoption resistance, especially in the all-important consumer market.
Due to the relatively high cost, the only component of the industry clearly adopting thermocompression bonding is the advanced memory segment, such has hybrid memory cube (HMC) and high bandwidth memory (HBM). The rate of adoption for applications processors, GPUs and the like may depend on the rate at which throughput and cost can be improved.
Thermocompression bonding can be segmented into two different processes. The first process differentiation is whether the underfill is pre-applied before the semiconductor chip is mounted or not. Pre-applied underfill comes either as a film applied to the die or as a paste applied to the substrate. In both cases the underfill must not only create a void-free bond, but also provide flux to remove oxide on the solder caps. The alternative process is thermocompression â€“ capillary underfill (TC-CUF) where the die is underfilled in the same way as std flip chip,except that the underfill process is much more challenging because of the more narrow bondline of a typical thermocompression bonded device. In TC-CUF, flux can be applied either by dipping the die into flux before bonding, or applying flux to the substrate.
A K&S cost-benefit analysis of a C2 (copper pillar bump) TC bonding process was used to look at the total packaging cost. Besides enabling higher I/O counts and finer pitch interconnections through better control of the stress and warpage, the actual bonding process is just a small contribution to the overall assembly cost. K&S shows that the incremental assembly cost adder for thermocompression bonding is actually rather small in a high UPH TC bonder. The hurdle to wide-spread adoption of the TC bonding is more likely the initial capital expenditure associated with buying new equipment when depreciated infrastructure already exists for mass reflow processes. Adoption of the technology will therefore be driven by technical need and market forces. TC bonding will enable higher I/O counts and finer pitch interconnections than traditional interconnect methods through better control of the stress and warpage between devices and the substrate. Once the infrastructure is established, they predict that the cost will decrease directly proportional to throughput and they have demonstrated that throughputs of 1000uph are possible.
Amkor / Qualcomm
Doug Hiner in a joint presentation between Qualcomm and Amkor presented â€śMulti-Die Chip on Wafer Thermo-Compression Bonding Using Non-Conductive Filmâ€ť. Non-conductive films have been in development as a replacement to the liquid preapplied underfill materials used in fine pitch copper pillar assembly.
Several assembly methods are available for chip on wafer assembly including: (1) traditional chip attach with mass reflow (MR) and capillary underfill (CUF), (2) thermo-compression
bonding (TCB) of copper pillar interconnects using nonconductive paste (NCP) underfill (TCB+NCP), and thermocompression bonding of copper pillar with non-conductiveÂ film (NCF) underfill (TCB+NCF).
The TCB+NCP process carries concerns with the underfill time on stage which prevents the dispensing of the NCP material across the wafer prior to the chip bonding process. This constraint effects process costs significantly. The TCB+NCF process to date have not met the cost/benefit needs of the industry. NCF assembly provides significant improvements in the design rules associated with die to package edge, die to die, and fillet size. The NCF process also resolves the time on stage concerns associated with the NCP process by laminating the NCF material to the bonded die instead of to the interposer or receiving wafer surface.
Development has proven the feasibility of a multi-die (gang) bond chip on wafer assembly process. Key assembly steps have been validated and major issues have been mitigated through optimization of materials and process parameters. A scale up phase of development has been initiated which targets the bonding of 8 die (4 units) in a chipÂ on wafer format. Assembly cost of ownership estimates (OSAT) suggest cost parity between 8-die gang bonding and traditional mass reflowâ€¦
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it seems that there is a strong trend towards wafer based stacking in image sensor production. It seems that for example Sony is capable to stack a ‘photodiode-array-layerâ€™ on top of a ‘logic, ADC…â€™ layer. It seems that they reach ‘1 interconnect per pixelâ€™ between the layers, so a pitch of <2 Âµm. It seems that they even use different process technology for the different layers. To me this type of waferstacking seems to be more attractive in volume production than chip based stacking. What is the reason why memory manufactureres do not chose wafer stacking but go for TCB type of chip stacking like HBM and HMC?