Insights From Leading Edge

IFTLE 247 ECTC part 3: More Thermo Compression Bonding from Intel and ASM

By Dr. Phil Garrou, Contributing Editor

In IFTLE 245, we looked at some of the key thermo-compression bonding (TCB) papers at ECTC. Is there any question that TCB is real and will be the next big bonding technology ? This week, more coverage on this very important new assembly process from Intel and ASM.

Intel & ASM – TCB for fine pitch Flip chip (C2)

Intel introduced TCB into high volume manufacturing in 2014. As substrate and die become thinner and solder bump sizes and pitches get smaller, the thin organic substrate tends to warp at room temp and as the temp is increased during the reflow process. The thin die can also demonstrate temperature dependent warpage, which can come into play during the reflow process. The extent of warpage of the substrate and die at high temperatures can overcome the natural solder surface tension force leading to die misalignment with respect to the substrate, resulting in tilt, non-contact opens (NCO) and in some cases solder ball bridging (SBB). The figure below shows shows these various defects.

C2 defects

In the Intel TCB process, the substrate with pre-applied flux is held flat on the hot pedestal under vacuum. The die is picked up by the bond head, held securely and flat on the bond head with vacuum. After the die is aligned with the substrate, the bond head comes down and stops when the die touches the substrate. A constant force is then applied while the die is heated up quickly beyond the solidus temperature. As soon as the solder joint melts, the die is moved further down (solder chase) to ensure all solder joints are in contact. The die is held in position allowing the solder to reflow completely, and to wet the bump pads and copper pillars. While the solder is still in the molten state, the bond head retracts upwards controlling the solder joint height. The bond head then releases the vacuum holding the die and moves away as the solder joints have solidified. The major process parameters, i.e temperature, force and displacement are continuously monitored during the TCB bonding process.

A schematic of the bonding tool is shown below.


Large differences in the CTE between the organic substrate and die results in different magnitude of expansions when heated which can lead to serious bump offset at corners. To minimize the thermal expansion mismatch, the substrate is processed at a lower temperature (e.g. 140ºC) while the die and solder is rapidly heated up for reflow and cooled down for solidification using a pulse heater with heating ramp rate exceeding 100ºC/s and cooling ramp rate exceeding 50C/s. This reduces the heat transfer to the substrate. The bulk of the substrate can remain at low temperature and does not expand extensively.

ASM – High Throughput Thermal Compression Bonding

In another ASM paper on TCB, they examined what they call liquid phase contact (LPC) TCB. The goal is to increase the throughput of the TCB process. Process flow is shown below. Flux is printed or sprayed on the substrate. Then the bonding head picks up a die from the carrier at an elevated temperature, but below the solder melting point. Hen the bonding head is heated up to a temperature higher than the solder melting point and the chip is aligned with the substrate. The chip is then contacted and wetted on the substrate at a predetermined bonding height. After a predetermined bonding time, the bonding head can move is cooled down to a temperature below the melting point of solder.



They claim this results in attachment of 1200 units/hr vs 600 for the std. TCB flux process.

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One thought on “IFTLE 247 ECTC part 3: More Thermo Compression Bonding from Intel and ASM

  1. Dev Gupta

    The Intel TCB process strategy & tool described looks much like the first micro bump TCB process developed 20 years ago at Motorola just 3 miles north of Intel Chandler. The Motorola process was developed to replace costly WB ed GaAs PAs going into Mobile Phones by FC-TCB of GaAs PAs on organic substrates. For GaAs FC actually reduced cost over WB. For details of the Motorola process see my papers at ECTC, ISHM and ITAP circa ’94 – ’95.


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