The IMPACT conference claims to be the largest gathering of packaging and PCB professionals in Taiwan. It is organized by IEEE CPMT, ITRI, IMAPS Taiwan and the Taiwan Printed Circuit Association. The Technical Chair for IMPACT 2015 is CT Liu, of ITRI.
Charlie Lu of Altera discussed his reasoning for the new term â€śViBâ€ť to describe Via-interconnect Ball-Grid-Array.
Traditionally we all learned that there are three types of interconnect: WB, FC and TAB. Lu defines ViB as a ball-grid-array package whose chip-to-package electrical interconnect is achieved by direct interconnection through the vias. Some wafer level packages and fan-out packages, he contends, belong to this category.
Traditionally, chip-to-package interconnect is done by wire bonding (WB), flip-chip bonding (FC), and to some extent, tape-automatic bonding (TAB). There are two steps for via-interconnect process: (1) via formation and (2) via filling or via bottom and sidewall metallization. Via formation could be done by laser ablation or photolithography process, or by other techniques. Via filling and metallization is usually done by mixed techniques of Ti/Cu sputtering and Cu or Ni/Cu plating. Thus, the process of via-interconnect technology is unique from that of WB, FCB, and TAB.
Lu compares the interconnect technologies in the table below.
The industry has begun using the term WLP for so called fan in packages fabricated on wafer, â€śFO-WLPâ€ť for fan out packages formed from reconstituted wafers, and â€śFO-PLP for fan out packages formed by panel level processing. Lu correctly points out that all packages except fan in WLP are FO packages. He prefers the term ViB as a category to cover both FO-WLP and FO-PLP. If it is necessary to spell out the process applied for a given ViB, an additional suffix could be added, like ViB-D, D stands for â€śdryâ€ť, meaning that the ViB is made by wafer Fab-like process. Likewise ViB-W means the ViB is processed by â€śwetâ€ť process, i.e. PCB-like process. It is no longer necessary to emphasize a package is fan-out or fan-in, because WLP already implies itself a fan-in package, apart from WLP, all others are fan-out packages.
Those of you who follow IFTLE closely know Iâ€™m a stickler for nomenclature and not a fan of terms like 2.1D which have no real meaning or â€śinterposerâ€ť since all packages are interposers. In this case Lu is attempting to clarify the categories and I can see some logic in his presentation. Whether we all pick up on ViB or not in the end will depend on all of you.
iNEMI updated their program on â€śrecent trends in package warpageâ€ť. Below we see a comparison of the warpage for various packages with various pretreatments.
- Dynamic warpage of POP package varies according the construction.
- There is insignificant dynamic warpage difference between â€śAs Iâ€ť vs Bake and MET.
- Majority of the POP package received kept the high temperature warpage below 100um.
- There is insignificant dynamic warpage difference between â€śAs Isâ€ť vs â€śBakeâ€ť and â€śMETâ€ť.
- Majority of the POP package received kept the dynamic warpage below 100um.
- There is no observable dynamic warpage difference between As Is vs Bake.
- Different Lid attachments can yield different dynamic warpage characteristic.
- Ceramic substrate with Lid demonstrate similar dynamic warpage behavior as like organic substrate but with lower magnitude for the package size considered.
- The effect of â€śBakeâ€ť and â€śMETâ€ť on dynamic warpage is more apparent in PBGA package.
- The â€śBakeâ€ť generally shows lower high temperature while â€śAs Isâ€ť and â€śMETâ€ť shows the tendency to elevate the warpage by 20-50um. Take note that this depends on the mold material used.
Max Lu, deputy Director of SIliconware, discussed WLP innovations such as molded WLCSP, Fan-Out WLP and NTI (No TSV interconnection).
Potential for greater board level reliability.
Passes: component level â€“ 1000hr TCT ; 96hr HAST and 1000hr HTS PASS
Board level â€“ 1000x TCT cycle and 30X Drop test.
Thinner FOWLP results in thinner PoP packages. Passes: component level â€“ 1000hr TCT ; 96hr HAST and 1000hr HTS PASS and Board level â€“ 500x TCT cycle and 30X Drop test.
No TSV Interconnect (NTI) Platform
SIliconware was one of the first to describe a chips last interconnect technology which they call SLIT (see IFTLE 215, â€śSTATS Acquisition; Will SLIT replace TSV?â€ť).
SPIL proposes the merits of NTI Platform are:
- Shortening interconnection distance than traditional TSV interposer.
- Reducing interposer process cost without TSV related process cost.
- Processing by all existing MEoL/BEoL equipment.
The following shows the unit operations done by SPIL and those done in foundry.
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