By Dr. Phil Garrou, Contributing Editor
Continuing our look at the 2015 IMAPS Conference.
Advanced packaging has increased in complexity over the years, transitioning from single to multi die packaging there are several platforms now available as summarized by Beica of Yole in the following figure. When choosing a package solution, typically the most mature and established will be considered first.
When looking at flip chip ~ 37% of the cost is attributed to the substrate. The substrate also increases the thickness of the package.
Fan out packaging offers increased I/O but also a thinner package since the substrate is not required. Initially limited to eWLB licensees from Infineon (Nanium and STATSChipPAC) the market is expected to explode in the next few years as ASE, SPIL, Amkor TSMC and DECA bring fan out capacity online.
Yole’s Ivankovic compared expectations for glass/silicon interposers vs polymeric substrates. Glass interposer technology is still immature. Polymeric sub 10um L/S substrates are promising but need cost reduction and further L/S reductions. The sweet spot for silicon interposers appears to be up to ~ 3/3.
IFTLE feels that silicon interposers with coarser L/S can surely be manufactured but will not compete on a cost basis. A substrate technology gap exists between 10 and 1um. This will be where the battle for business will be fought.
Chen of ASE escribed their new Fan out Chip Last Package (FOCLP) which they see as a low cost alternative to eWLB FOWLP solutions. Copper pillar bumped die are mass reflowed onto a low cot coreless substrate, followed by overmolding, which also serves to underfill the die. The Cu pillars allow die connection at 50um or below, negating requirement for RDL n the die. The Cu pillars are bonded to one side of the copper trace (down to 15um L/S) and solder balls are directly bonded to the other side. This makes the “substrate” be effectively as thick as the copper in the traces and allows the final package to be as thin as 400um. Implementation with multiple die, inclusion of passives and 3D structures can all be implemented.
STATSChipPAC – High Density eWLB
Currently eWLB devise are used in baseband processors, RF transceivers, power management ICs, NAND memory controllers, on 2 node and ramping on 20nm. In a number of cases STATS reports a 20-40% reduction in package size and a 50% volume reduction due to its slim form factor.
STATS presented their work on with Qualcomm defining eWLB technology with high density ( 2/2 L/S ) and multilayer RDL. Their test structure contained 3 layers of RDL with 2/2, 5/5 and 10/10um L/S.
These structures were built and passed std JEDEC reliability testing.
Nanium – Advances in eWLB
NAnium described new developments in eWLB technology. Kroehnert indicates that the first eWLB based products have been qualified for wafer level SiP and WLPoP with embedded multi die, discrete passives, already packaged components sensors and optical elements.
As thin 300mm reconstituted wafers are not stable enough to be handled in traditional equipment, temporary bonding of recon wafers was developed. They found significant impact from bot the temp bond adhesive and the carrier composition.
The majority of work being done is to enable higher density integration:
– finer L/S
– multilayer RDL routing
– multi die placement with smaller inter chip distances
For all the latest in 3DIC ab=n other advanced packaging stay linked to IFTLE…