ByÂ Dr. Phil Garrou, Contributing Editor
Samsung announces 4GB HBM2 DRAM
Samsung Electronics announced that it has begun mass producing the industryâ€™s first 4-gigabyte (GB) DRAM package based on the second-generation High Bandwidth Memory (HBM2) interface, for use in high performance computing (HPC), advanced graphics and network systems, and enterprise servers. [link]
The newly introduced 4GB HBM2 DRAM, uses Samsungâ€™s 20nm process technologyÂ and is reportedly more than seven times faster than the current DRAM.
The 4GB HBM2 package is created by stacking a buffer die at the bottom and four 8-gigabit (Gb) core dies on top. These are then vertically interconnected by TSV holes and microbumps. A single 8Gb HBM2 die contains > 5,000 TSV holes, which is more than 36 times that of a 8Gb TSV DDR4 die, offering a dramatic improvement in data transmission performance compared to typical wire-bonding based packages.
Samsungâ€™s new DRAM package features 256 GBps of bandwidth, which is double that of a HBM1 DRAM package. This is equivalent to a more than seven-fold increase over the 36GBps bandwidth of a 4Gb GDDR5 DRAM chip, which has the fastest data speed per pin (9Gbps) among currently manufactured DRAM chips. Samsungâ€™s 4GB HBM2 also enables enhanced power efficiency by doubling the bandwidth per watt over a 4Gb-GDDR5-based solution, and embeds ECC (error-correcting code) functionality to offer high reliability.
Samsung also plans to produce an 8GB HBM2 DRAM package in the next 12 months. Offering designers a 95 percent space savings vs GDDR5 DRAM.
Samsung announced that production volume of HBM2 DRAM will increase over the remainder of the year.
The second-generation HBM (HBM2) technology is outlined by the JESD235A standard. It uses 128-bit DDR interface, 1024-bit I/O, 1.2 V I/O and core. Just like HBM1, HBM2 supports two, four or eight DRAM devices on a base logic die (2Hi, 4Hi, 8Hi stacks). HBM Gen 2 expands capacity of DRAM devices within a stack to 8 Gb and increases supported data-rates up to 1.6 Gb/s or even to 2 Gb/s per pin.
Continuing our look at the 2015 3D ASIP Conferenceâ€¦
Brandon Prior of Prismark addressed the â€śStatus of 2.5/3D and other high density packaging technologiesâ€ť.
2.5D / Silicon Interposer is an effective fine-pitch solution to provide >10,000 die-to-die connection. Currently used for:
â€“ ASIC/FPGA die partition
â€“ GPU/CPU/ASIC + memory
â€“ For L/S <2ÎĽm and vias <5ÎĽm, Si interposer is the only available approach
- Several notable production developments with 2.5 and 3D technology in 2015
â€“ All major DRAM players with production capability of TSV memory stacks; but focus remains on â€śnear memoryâ€ť requiring extremely high bandwidth
â€“ Si Interposer adoption by AMD for â€śgaming enthusiastâ€ť GPU
â€“ Continued work with TSV for Image and other sensors for backside access
- Increased adoption of 2.5 and 3D TSV dependant on cost and alternatives
â€“ Si Interposer most relevant to server/telecom CPU and ASIC products
â€“ TSV for portable processors still under review, but LPDDR5 is more likely
- Companies such as Sony, Toshiba, Aptina, ST have been shipping image sensors with TSV for back side access since 2009/2010
- Sony is first to ship using die stacking â€śhybridâ€ť approach in 2012/2013; economical only for 8 â€“ 13MP designs
ADVANCED PACKAGE SUBSTRATE DESIGN RULES
- Substrate technologies continue to progress
â€“ 10-12ÎĽm L/S in HVM for MPU
â€“ 8ÎĽm L/S capabilities in process at Kyocera, Ibiden, Shinko and others
- Sub-5ÎĽm on organic is a challenge
â€“ RDL technologies used in FO-WLP or Si Interposer are looking to displace build-up substrates
- Ibiden and Shinko working on â€śorganic interposerâ€ť
â€“ Internal qualification now down to 2ÎĽm L/S and vias 10-25ÎĽm
â€“ Yield remains a challenge, so Si Interposer remains compelling alternative
FO-WLP MARKET STATUS
- Expectation is that Apple will proceed with TSMC InFO FO-WLP for A10 in 2016
â€“ Tool orders and capacity seen in supply chain
â€“ Speculation on second location/source being required
- OSATs see uptick in interest for products outside application processor
â€“ OSATs: JCET/STATS, ASE, SPIL, Amkor, Nanium, PTI, DECA and Inotera
â€“ Possible Customers: Marvell, Qualcomm, Mediatek, Dialog, Renesas, Infineon,
Freescale, Avago, Analog, Spreadtrum, Maxim, HiSilicon
- Most focus on smaller die/packages: 3×3 to 8x8mm
â€“ â€śLarge die FO-WLP remain too expensive and yield challengedâ€ť
â€“ Expect 1 and 2 die packages with hundreds of I/O in 2016 from multiple applications and companies
â€“ Most production of FO-WLP focused on 1-3 layer RDL at 5-15ÎĽm L/S.
â€“ 300mm reconfigured wafers remains dominant approach for now
- Intel and Samsung remain skeptical of FO-WLP
â€“ At this time, neither have plans to install fan out capacity
â€“ Not seen as cost effective means to make a thinner package
Northrup Grumman / DARPA DAHI Program
After DARPA program Manager Dan Green gave an introductory presentation on the DARPA goals for DAHI (Diverse Accessible Heterogeneous Integration) [see IFTLE 206, â€śCOSMOS and DAHI Herald the Era of 3D Heterogeneous Integrationâ€ť ] Augusto Gutierrez-Aitken detailed DAHI activity in NGAS.
DAHI seeks to create circuits from various CMOS nodes with SiGe, GaN and/or InP.
They have developed a basic foundry infrastructure allowing external design teams to generate multiple technology heterogeneously integrated circuits
- Developed a process to integrate multiple compound semiconductor technologies to CMOS wafers
- Demonstrated three-technology integration between IBM 65nm CMOS, NGAS TF4 InP HBT, and NGAS GaN20 HEMT
- Demonstrated integration of third-party technology
A typical NGAS DAHI flow is shown below.
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