By Dr. Phil Garrou, Contributing Editor
Finishing up our look at the 2015 3D ASIP, conference we’ll look at the presentations from some of the memory suppliers and users.
Higashi form Toshiba discussed TSV technology for NAND flash. IFTLE did not take this to be a product announcement, but rather a technology status report.
We are all aware that flash faced major obstacles continuing normal scaling so it recently moved to monolithic stacking. NAND scaling will stop its planar 2D approach at 10 nm. All market players have developed 3D NAND technologies where the memory cells are now vertically aligned. There are many competitive monolithic transistor stacking technologies reported as shown below.
Higashi proposes that TSV flash will be required to achieve the high performance ( low latency and IOPS/W ) and low power required for performance SSD.
23Gb and 256Gb prototype chip stack is shown below.
At the 2015 Flash Memory Summit, they showed a prototype SSD using this TSV based NAND.
It was proposed that the first application may be data center servers.
During Tom Gregorich of Micron’s discussion on “Challenges in the Development and Deployment of Ultra High‐Performance 3Di DRAM Systems,” he noted that the ASIC to DRAM interface s what controls the bandwidth and power usage. The Micron HMC uses SERDES interface which is great for performance but in order to make it in consumer products they will need a new interface type to drop pricing.
AMD / Hynix
3D ASIP supporters Bryan Black of AMD and Minh Suh of Hynix updated the 3D ASIP audience on the status of Hynix HBM memory stacks and the status of the first graphics product to hit the market with TSV stacked HBM memory, the Radeon R9 Fury Series GPUs.
The interposer is made by UMC in the 300mm Fab 12 foundry (UMC) in Singapore. UMC is reported to have entered into volume production very recently (July 2015).
Hynix compared current HBM1 to the soon to be released HBM2 in the following slide.
The feel that the new generations of HBM will expand their use into more market segments.
The Patti architecture and manufacturing process are quite different from the 3 main DRAM suppliers. In terms of architecture he separates not only the control functions but also has a separate layer for the I/O. This allows them to deliver “the right I/O for every need.”
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