ByÂ Dr. Phil Garrou, Contributing Editor
The annual SEMI ISS (Industry Strategy symposium) meeting took place as usual in January in Half Moon Bay CA. What was different was something that IFTLE has been predicting for while: â€śIn the future when the front end community runs out of advances they will begin to focus on assembly/packaging.â€ť Wellâ€¦the future is NOW.
Intelâ€™s Corporate VP Babak Sabi got on the packaging bandwagon with his presentation â€śMaintaining the IC Scaling Edge through Packaging.â€ť
He showed the following detail on their Altera FPGA demonstrator using their Intel EMIB technology [for technology detail see IFTLE 209 â€śSamsung announces TSV based DDR4; What is Intel eMIB?â€ť]
The following is an interesting comparison of Intelâ€™s understanding of feature size vs substrate technology.
Mike Campbell of Qualcomm focused on â€śmodule and 3D packaging as the new integration path for semiconductors.â€ť
Showing the following example for future SiP heterogeneous integration in a 2.5D format and the required enabling technologies.
Dan Tracy â€“ Dir of SEMIs Industry research group also focused in packaging in his presentation â€śItâ€™s All About Packagingâ€”In this Materials World That We are Dealing Withâ€ť using materials supplied by TechSearch Inc.
Mobil products are certainly the driver for packaging.
He offered the following comments for individual markets:
– $1.2B market size
– stable Japanese supply base
– focus on warpage control, CTE, low moisture, low ionics
– molded underfill (MUF) for CU pillar FC
– high TC and high V apps emerging
– global mkt $250MM
– currently 30+ suppliers [note from IFTLE so this is ripe for consolidation]
– new resins and fillers for fine pitch requirements
– No flow applied prior to chip placement â€“ both liquid and film based
– use of mold compound as underfill
– increased use of board level underfill for CSP, BGA, WLPs
Wafer Level Dielectrics
– $90MM market
– requirements for new material entrants include – low temp cure, low warpage
Handle Jones of IBS presented the following projection for wafer level packaging which he claims is being driven by Apple. Note he projects that we will be approaching 1MM WLP wafers/month by 2020.
Jones also noted that with the acquisition of STATSChipPAC, JCET has become the worlds 3rd largest OSAT.
For all the latest in 3DIC and other advanced packaging, stay linked to IFTLEâ€¦