By Dr. Phil Garrou, Contributing Editor
The IMAPS Device Packaging Conference was once again held in March in Arizona. Here is a look at some of the more interesting papers from the conference.
AMKOR – 2.5/3D Readiness
In Amkor’s presentation on 2.5/3D readiness, the following slide showing product qualifications was of special interest.
2.5D & 3D product qualification data is shown below:
GlobalFoundries TSV Readiness
GlobalFoundries TSV technology is qualified and ready for HVM ramp for all <28nm nodes Fab 8. Std TSV size is typically 5 x 55um.
Thermo-compression bonding is used for assembly.
- First, thin TSV die bonded chip to substrate (CoS) using non conductive paste (NCP)
- Top dies then bonded chip to chip (CoC) during 2nd bond on top of first stack
- TC-NCP process is used to minimize stress on ULK layers during cool down
Warpage characterization is critical during design and reliability phase of development along with production yield improvement.
- 3 different backside passivation layers were assessed in terms of impact of film stress on warpage
- Backside passivation film stress does not play a big role in overall package warpage
- Top Die Thickness impact on warpage
- Package level warpage in the order of 125um was measured at peak temperature for 100um thin top die
- With 260um thick top die package warpage was reduced to 80um at peak temperature
- Packages with 100um top die and thus increased stress / warpage clearly showed cracks appearing in the Cu pillar joints. Thus higher warpage clearly leads to degraded electrical performance of copper pillars in the corners of the package
While most of us were focused on 3D stacking of memory chips, CEA Leti was studying the stacking of capacitor chips. Using the PICS capacitor technology of IPDIA, Leti demonstrated that a smaller thin film cap footprint could be achieved if silicon caps are stacked and connected in parallel.
Several attacking technologies are proposed including TSV and more traditional WB.
Various packaging solutions are presented including a molded version (shown below) but IFTLE strongly disagrees the inference that such packages can withstand near 400C since IFTLE has expressed many times that thermal stability needs t be determined from isothermal TGAs NOT ramp TGAs like the one show. Ramp TGAs tend to highly exaggerate the thermal stability of the samples in question, for instance epoxy mold compounds are NOT stable at anywhere near 400C.
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Dear Dr Garrou,
As the author of the presentation from CEA-Léti, I would like to respond to your comments and clarify some points.
Neither in the presentation nor in the short paper we claim that the epoxy package can withstand near 400°C. Our component aims at operating at 220°C (see this specification earlier in the presentation) which is the temperature of the isothermal TGA (lower graph) we plotted in addition to the ramp TGA (upper graph). We totally agree that the thermal stability of a polymer cannot be determined from a ramp TGA only, and we did NOT do so.
You are correct, on second reading you do not say that the materials is stable at 400+ C. My problem is with ramp TGA data is it has no bearing on any microelectronic packaging reliability, whereas isothermal data does. You rightly show the isothermal data as well so I take back my statement that it “inferrs” stability.