Insights From Leading Edge

IFTLE 295 Advances in FO-WLP at 2016 IEEE ECTC

By Dr. Phil Garrou, Contributing Editor

Continuing our look at IEEE ECTC 2016. Let’s examine some of the activity in the FOWLP arena.


At the recent ECTC conference, Bill Chen of ASE proposed categorization of fan out packaging.

While the initial driver for fan-out packaging like the Infineon e-WLB was to increase available IO for niche baseband applications, the main driver now is clearly to achieve multi chip packaging.



Chen now proposes we categorize FOWLP options as follows based on chips first, chips last, multichip or stacked chips (PoP):


DECA – Adaptive patterning for FO WLP

FO-WLP enables size and performance capabilities similar to Wafer-Level Chip- Scale Packaging (WLCSP), while extending the capabilities to include multi-device system-in-packages, with lower costs than 2.5D interposer technologies. But – Adopting these new technologies for single die and multi die system-in-packages requires more advanced design methodologies and tools than traditionally used in traditional WLP.

In a fan-out process the key step is the creation of a reconfigured wafer or panel. First copper studs are formed on the native device wafer over the bond-pads, and then the wafer is singulated. A pick-and-place machine then attaches the dies face-up to a carrier with a temporary adhesive. Then, the carrier and dies are over-molded, the temporary adhesive is removed, and the front of the panel is ground to reveal the copper studs. After this process, called panelization, a first via layer (VIA1), redistribution layer (RDL), second via layer (VIA2), and under-bump metallization (UBM) are formed using processes similar to WLCSP.

Two main challenges prevent widespread adoption of wafer-level fan-out technology are warpage and die shift during processing. Warpage is caused by the mis-matched CTE between mold-compound and silicon and can be addressed using structural approaches, such as the fully molded structure, or by tuning process parameters. Die-shift is the accumulation of die position error from chip-attach tolerances and movement during over-molding. Tuning process parameters such as pick-and-place force can help minimize shift, and movement due to molding is often predictable enough to compensate for during chip-attach. However, the total die shift can still range from 30 μm to 45 μm with rotation up to 0.3°on a high-throughput machine.

The die-shift problem has limited traditional FO-WLP from widespread adoption. In order to meet industry requirements, FO-WLP must be processed with high-throughput chip-attach machines, typically resulting in shift distributions that cannot be handled by traditional processes. Additionally, these processes cannot handle finer pitch connections to the die with wider shift distributions

The DECA technology derived to do this is called “Adaptive Patterning”. In this manufacturing process, an optical scanner is used to measure the true position of each die after molding, and a uniquely generated fan-out design is applied to each package. One design technique, adaptive alignment, shifts and rotates the first via and RDL layer to match the die location. Another technique, adaptive routing, utilizes a fan-out RDL design with sections removed near vias that contact the die. The final RDL connections to the die are generated by an auto-router after the true die locations are known.

In the case of adaptive patterning, the design rules specify the maximum die-shift for which the design can be adjusted. For both cases, a simple approach limits the die-shift to a range of X, Y, and θ values (e.g. −30 μm to 30 μm and -0.3°. The table below shows the magnitude of shift possible from rotation alone on several package sizes.


By adapting to die-shifts that are an order of magnitude larger than can be tolerated by traditional processes, this technology solves the last major industry challenge to adoption of fan-out packaging. The design rules for adaptive patterning are more complicated than traditional rules; however, this may be required for designs with high density interconnects and scarce routing space.

Siliconware – Fine Pitch RDL for High Density 2.5D

The original purpose of the Redistribution Layers (RDL) was to assist in the adaption of metal bumping and flip chip packaging technologies, by the addition of the metal and dielectric layers onto the wafer surface to re-route the legacy designed irregular peripheral I/O layout, into a new area array bond pads layout to facilitate a balanced metal bumps and flip chip bonding. The redistribution layer technology required polymeric thin film (e.g. BCB, Polyimide, PBO) as insulator and a semi-additive metallization scheme (often Cu pattern plating).

RDL technology, has extended its application into advanced packaging technologies, such as fan out wafer level packaging (FO WLP) and various TSV-less, substrate-less multiple chip integration, that to drive the cost effective miniaturization of system-in-package (SiP) application. The Cu RDL that in production, the line width/ spacing are 10 μm/10 μm or pitch of 20 μm .

The capability for fine pitch and multi layer RDL must be established at OSATs because the market is currently driving towards multiple chips integration and SiP applications. Furthermore, it is more difficult for the L/S < 2um due to there is no sufficient process window of lithography process.

While scaling from 10 to 3 μm poses no significant technical difficulties with existing tools, as long as the Cu thickness are proportional shrunk to keep the width/ height aspect ratio, below pitch of 6 μm, it is difficult to make such fine pitch layers on top of other layers, since the topography of multiple RDL with any planarization, that is out of the depth of focus (DoF) range of 2 μm and 1 μm, and such 2 μm / 4 μm pitches, would be limited to the first RDL in the multiple RDL scheme.

Cu dual damascene technology are generally used in ICs manufacturing or silicon interposer fabrication. CVD dielectric films (Si oxide, Si nitride) are commonly used in the modern IC fabrication fab (90nm and beyond), and can be used for up to three levels of 1um Cu RDL .

A comparison between a Cu dual damascene process and traditional organic RDL process are shown below. The Cu dual damascene process can provide a flat surface with excellent topography and we can combine this advantage with traditional RDL process to resolve the surface topography issue for the multiple RDL layers. For example in 3 layers RDL structure, we can use one dual damascene layer and two organic RDL layers to reduce the TTV of surface topography and then satisfy the DoF requirement of photo-resist materials.


Cu dual damascene technology is a challenge for traditional bumping process and tools, especial for the lithography, Reactive-Ion Etching (RIE), Cu electroplating, and Chemical-Mechanical Planarization (CMP) steps. For the lithography process of Cu dual damascene, the key points are the opening dimension and profile of photoresist materials after the lithography process. Current development and research direction focus on the high resolution photo-resist materials and high numerical aperture (NA) exposure tools. The dielectric material of Cu dual damascene is generally silicon oxide (SiO2). In order to increase the oxide etching thickness accuracy, a thin silicon nitride (SiNx) film is deposited as stop layer between the oxide layers.

The figure below shows a silicon interposer structure with TSV and there are 3 dual damascene metal layers with u-pad in frond side of interposer and there is one RDL layer with C4 bumps on the backside of the interposer. The L/S are 1um and thickness 1um also for 3 dual damascene layers. And layers are connected by 0.5um diameter and 0.9um thickness via opening.


Hybrid integration of the fine pitch CVD RDL with polymeric dielectric RDL is shown in the figure below. It is a substrate-less package with 0.4mm pitch BGA balls; the package size is 15mm x 14mm with one CVD dual damascene RDL with 2/2um line L/S combined with two organic RDL with 5/5um and 10/10um line L/S.



The top die jointed with RDL by 40um pitch u-bump and molded by molded underfill (MUF) technology. The CVD oxide and nitride RDL 2/2um line L/S connected to organic RDL 5/5um line L/S by 10um via open which made by deep reactive-ion etching DRIE process. The second RDL contains 10/10um line L/S. This hybrid test vehicle passed open/short test after 96hrs of HAST, 1000 TCB cycles and 1000hrs of HTS.

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