Insights From Leading Edge

IFTLE 297 TSMC Describes UBM Free Fan-In WLCSP

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2016 ECTC Conference:


TSMC discussed their UFI (UBM-Free Integration) Fan-In WLCSP technology which they claim enables large die fine pitch packages.

Development of low-cost WLCSP for large die with high I/O count is desired for broadening its applications. Reliability issues including solder cracking and high chip warpage are known to be the main challenges for extending the die size of conventional WLCSP to more than 5×5 mm2 with ball pitch smaller than 350 um.

TSMC has discovered that by controlling the maximum strain location and optimizing materials, chip warpage and the stress between Si and the PCB can be reduced which improves both component and board-level reliabilities of WLCSP packages. Packages as large as 10.3×10.3 mm2 with both 400 and 350 um ball pitches have been developed.

UBM is used as an interfacial layer between the metal pad of the integrated circuit and the solder ball. The formation of UBM/solder intermetallic compounds (IMC) limits the board level reliability of the package due to the poor mechanical robustness of IMCs. When the die size is increased, stress increases which promotes cracking at the UBM/solder ball interface.

TSMC claims their UFI WLCSP fabrication cost is lower than conventional WLCSPs due to the elimination of the UBM. Removal of the UBM also reduces the thickness of the package by 30%.

The figure below compares the structures of a standard WLCSP vs the TSMC UFI WLCSP. In the UFI WLCSP, the solder balls are directly mounted to the Cu RDL followed by the polymeric PL (protection layer which secure the balls.


Very similar removal of UBM and subsequent thickening of the copper pad has been reported before by Amkor in 2010 [link]

TSMC simulation results showed the solder joint fatigue life decreases with increasing die sizes for both UFI and the conventional WLCSP. Predicted solder ball fatigue life was found to increases with decreasing die thickness. The authors suggest that decreasing the die thickness not only reduces the thermal expansion difference between the die and the PCB, but also causes the die to bend more under thermal loading. In addition, simulation results imply that solder joint creep strain for solder mask defined (SMD) structures is 72% higher than for non solder mask defined (NSMD) structures because of its reduced flexible solder joint height and the constraint of the solder mask. Thus they concluded that it is better to use NSMD type of PCB for UFI WLCSP. The use of NSMD structures to increase reliability has been known since the work of Bell Labs Ejim [ref]

TI Ejim et. al., “Reliability performance and failure mode of high I/O thermally enhanced ball grid array packages” Electronics Manufacturing Technology Symposium, 1998, p.323 – 332.

The UFI WLCSP passes all component-level tests and exhibited board-level thermal cycle life that is 1.4 and 2.3 times longer than that of the conventional WLCSP in terms of the first failure and the Weibull distribution, respectively. 10mm UFI WLCSP have passed component-level reliability tests suchas TCB1000, uHAST96 and HTS1000, and board-level reliability tests of TCG500 and drop tests. 

To demonstrate the possibility of higher interconnect density, they fabricated UFI- WLCSP with multiple RDL layers. The package with two RDL layers had die size of 10.3 x 10.3 mm2 and ball pitch of 350 um. The structure is shown below. Again such structures passed all component level reliability testing.


Tohoku University – Interconnect Impact on 20um thick DRAM Chips

The effect of thermo-mechanical stress originating from CuSn μ-bumps and Cu TSVs on the retention characteristics of 20- μm-thick, vertically stacked DRAM memory chips. They determine that there is 50% probability that data retention period decreases by 47% for the DRAM chip having thickness value of 20 μm as compared to the retention period of 200 μm-thick DRAM chip.

Back-end-of-line (BEOL) processes on ultra-thin dies/wafers might cause severe degradation to device performance, due to deteriorated mechanical strength and lattice defects, back-side metal contamination, thermo-mechanical stress caused by TSVs and μ-bumps, local mechanical stress

induced on active Si near m-bump region, etc. They the thermos-mechanical stress present in the DRAM dies with thickness values varying from 200 μm down to 20 μm using micro-laser Raman spectroscopic techniques.

Retention time data obtained for a 50 μm-thick DRAM die at two different positions respectively 15.5 μm and 0 μm from the KOZ of TSV. Before annealing the stacked die, we observed similar retention time values for both the macros. While after annealing at 300 °C, irrespective of position they observed reduction in DRAM retention time at the area closer to the KOZ.

Upon reducing down the DRAM chip thicknesses to 20 μm from 200 μm, the retention time is nearly halved at the cumulative probability of 50 %. After annealing at 300 C, a compressive stress value of -200 MPa caused by Cu-TSVs was found as the remnant stress at the periphery of the keep-out-zone, and faded quickly by moving away from the keep–out-zone. Retention time deterioration was found to be influenced by the thermo-mechanical stress caused by TSVs. A large amount of tensile stress was induced on the back-side of DRAM chip at right above the CuSn μ-bump region.

Tohoku 1

Brewer Science – Temporary Bonding Materials

IMEC, Brewer Science and Suss gave a presentation on the status of temporary bonding materials.

The first-generation product was WaferBOND® HT-10.10 thermoplastic bonding material. The debonding approach was based on the re-melt of the bonding material at elevated temperature and mechanical slide-off of the carrier. The technique poses some challenges including:

  • Debonding is usually performed at an elevated temperature, in the range of 200°C or higher, which prevents the integration of low-melting-point solder materials.
  • Shear force increases with the carrier slide-off speed.

The second-generation product ZoneBOND® 5150 is based on a room temperature debonding. A short chemical dissolution of the bonding material on the wafer edge is required before mechanical debonding. The thin wafer is put on dicing tape, ensuring mechanical support throughout the process. The carrier substrate is then removed mechanically in a perpendicular direction as opposed to the thermal slide debonding approach.

To further reduce the process cost, a third generation of materials, BrewerBOND® 305 , has been explored. They have eliminated the need for dual zones on the carrier substrates . Thus debonding no longer requires any chemical treatment reportedly simplifying the process and resulting in a cost reduction of 25%. A summary of the three generations of processes and key challenges can be found in the table below.

Brwer 1

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