ByÂ Dr. Phil Garrou, Contributing Editor
Continuing our look at IEEE ECTC 2016:
IME â€“ Thermo Compression Bonding of 20Âµ Pitch Copper Pillar Bump for 3DIC Stacking
Throughput is limiting the adoption of 3D IC stacking processes although 3D IC has many advantages in shorter communication lines, lower electrical parasitic and lower package footprint. Thermal compression bonding (TCB) of a chip stack done one by one, it takes long cycle time to complete a 300mm wafer. Typical TCB bonding with bump pitch of 50-100Î¼m takes 14-16 sec per chip and more than 22 hours for a 300mm wafer with 1440 dies x 4 layer stacking. A significant improvement on the throughput is needed for high volume manufacturing.
IME has developed a 20Î¼m pitch micro-bump array assembly process with throughput of 1200 UPH (or 3 sec/chip) and bonding accuracy <2um by using two-step C2W bonding. The C2W is carried out in two steps where in the first step chips are temporary tacked on the wafer with planarized wafer level underfill, and in the second step, fully populated tacked chips on wafer are permanently bonded by using pressurized gas in a gang bond process. The gang bonder maintains chuck at constant bonding temperature. This two-step C2W process provides a new approach to solve the major concerns of the two step C2W bonding: (1) chips shifting during gang bonding, (2) pillar height variation causes gang bonding force non-uniform distribution among chips and (3) fine pitch (<30Î¼m) solder bridging causing electrically short.
A traditional gang bonder uses metal piston press on the top wafer but sine copper pillar bump heights are not uniform enough, a soft material layer is added on top of the chips to absorb chip height variations as shown below.
But the soft layer material and Si wafer have different CTEs, thus expanding differently during thermal processing . This non-uniform expansion causes horizontal force on chips resulting in chip misalignment. To overcome the chip shifting issue, a gas pressure bonder is used for gang bonding as shown below.
This solves the pillar height variations without chip shifting.
IBM Zurich â€“ All Copper Interconnect from Nanoparticle Sintering
IBM Zurich continued their reporting on the use of copper nano particles (nps) to form all-Cu flip chip interconnects based on pressureless low temperature sintering (~ 200 C).
It is generally agreed that an increase in current density is required to support the reduction in transistor size and supply voltage as well as 3D integration of integrated circuits. However, the current capacity in solder-based interconnects is limited due to electromigration. It is generally accepted that all-Cu interconnects should result in electrical interconnects with a higher current capacity.
Fully Cu interconnects can be formed by thermocompression bonding (TCB) of two flat Cu surfaces at high temperatures (350 C) and pressures. It is also known that the use of nanoparticles (nPs) at the bonding interface reduces the required temperature and pressure needed to form an interconnect, while also allowing for less stringent requirements for surface roughness.
In the IBM process, a Cu paste is applied between Cu pillars and Cu pads in a standard flip chip bonder. The assembly is performed at room temperature with a controlled low force. The interconnects are subsequently formed by sintering the Cu nPs in the paste at 200 Â°C in a batch oven under a reducing formic acid atmosphere.
However, large differences in electrical and mechanical properties of the tested sintered Cu foils compared to bulk Cu results as shown below. It is believed this is due to the porosity present in these nano copper interconnects. The shear strength of the nano copper interconnects was also significantly lower than standard Sn/Ag non lead joints [ 19 =/-5 MPa vs 65-75 +/- 10 MPa]
Attempts to use a bi modal distribution of nano and micro copper particles did not materially affect these results.
SK Hynix â€“ Characterization of Stacked Memory
The use of tremendous number of through TSVs and micro-bumps in a stacked package is a major worry to its manufacturers and users. DRAM chips with TSVs are thin and its micro-bump interconnection can be affected by the process conditions and materials selection. Copper, widely used for via filling, may bring about interconnect failures by Cu pop-up due to higher CTE than Si and transistor failures by its contamination into silicon lattices. Micro-bump joints are also of interest in terms of reliability. Thermal-compression bonding (TCB) is a common way to stack up multiple chips with TSVs and micro-bumps but insufficient bonding time can lead abnormal bump joints and various failure modes such as non-wet, brittle intermetallic compound (IMC) formation, bump cracking, head-in-pillar (HiP) joints etc.
Thermal characterization is also important in TSV stacked chip packages. High performance devices such as HBM packages need to be thermally evaluated. Any polymer layers between stacked chips may impede thermal flow and thus raise the junction temperature of each slice.
Fault isolation techniques are required to identify and correct any failure modes present. Options are compared in the table below.
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