Insights From Leading Edge

IFTLE 303 Sony Introduces Ziptronix DBI Technology in Samsung Galaxy S7

By Dr. Phil Garrou, Contributing Editor

It has been awhile since we last checked in on the CMOS Image sensor (CIS) community to see what the latest advances in packaging were [see IFLE 172 [link], 244 [link], 272 [link] and 278 [link].

For those that need to catch up on the technology roadmap, Toshiba was the first to commercially implement CMOS image sensors with backside TSV last technologies in 2007 ( this was covered thoroughly by my predecessor blog PFTLE which was unfortunately scrubbed from the internet when “Semiconductor International “ went out of business. This technology is well explained by CEA Leti [link].

Many of us stated in 2007 that further advances could be obtained by removing the CMOS circuitry to a separate layer and forming a true 3D chip stack, but the technology implementation had to wait while the industry first converted to back side imaging technology.

“Backside Imaging” – BSI

With a conventional front-illumination structure, the metal wiring above the sensor’s photo-diodes impede photon gathering. A back-illuminated structure (figure below) increases the amount of light that enters each pixel due to the lack of obstacles such as metal wiring and transistors that have been moved to the reverse of the silicon substrate [link].

Back side illumination


Back Side Imaging – stacked

The next generation, as expected, combined both BSI and stacking. Conventional CMOS image sensor technology creates the pixel function and analog logic circuitry on the same chip. The motivations for stacked chip CIS include: optimization of each function in the stack, adding functionality to the stack and decreasing form factor.

Since the pixel section and circuit section are formed as independent chips, each function can be separately optimized, enabling the pixel section to deliver higher image quality while the circuit section can be specialized for higher functionality. In addition, faster signal processing and lower power consumption can also be achieved through the use of leading process for the chip containing the circuits.[link]



So, where do things stand commercially?

The 2014 image sensor market was estimated by Techno Systems Research as shown below.




Sony is clearly leading in commercializing the latest CIS packaging technologies.

In 2012 Sony announced the Exmor RS, Stacked CMOS back-side illuminated sensor, where the supporting circuitry is moved below the active pixel section, giving ~ 30% improvement to light capturing capability [link 1] [link 2].

The first generation Sony BSI-Stacked chips employed via-last TSVs to connect pads from the Sony-fabricated, 90 nm generation CIS die to landing pads on a Sony-fabricated, 65 nm generation ISP. The die stack was partitioned such that most of the functionality of a conventional system-on-chip (SoC) CIS was implemented on the ISP die; the CIS die retained the active pixel array, final stage of the row drivers, and comparator portion of the column-parallel ADCs

Some of the biggest names in tech use Sony sensors: The iPhone 6 camera has a Sony sensor, as does the Samsung Galaxy S6, Motorola phones, Nikon DSLRs, and Olympus mirrorless cameras. [link]

Earlier in 2016 it was reported that there are two versions of the Samsung Galaxy S7. One has a Samsung stacked ISOCELL sensor (S5K2L1) and the other a special Sony stacked sensor (IMX260) [link].

The recent Chipworks teardown of the Samsung Galaxy S7 with a Sony IMX 260 revealed BSI stacked technology [link 1]. Furthermore it revealed the first reported use of the Ziptronix (now Tessera) Direct Bond interconnect (DBI) technology rather than prior oxide –oxide bonding with subsequent TSVs connecting through the oxide interface [link 2]. This BSI-stacked DBI technology is possibly the next step in the CIS roadmap.

The Chipworks cross-section (see below) reveals a 5 metal (Cu) CMOS image sensor (CIS) die and a 7 metal (6 Cu + 1 Al) image signal processor (ISP) die.  The Cu-Cu vias are 3.0 µm wide and have a 14 µm pitch in the peripheral regions.  In the active pixel array they are also 3.0 µm wide, but have a pitch of 6.0 µm. Note that in the images we’ve included we do see connections from the Cu-Cu via pads to both CIS and ISP landing pads.

Sony DBI



Omnivision was the first to sample BSI in 2007 but costs were too high and adoption was thus very low.

In 2015 Omnivision announced their OV 16880 a 16-megapixel image sensor built on OmniVision’s PureCel-S™ stacked die technology [link].


Samsung’s first entrant into stacked technology with TSV was also at 16MP with the Samsung S5K3P3SX in late 2014. The CIS die is face-to-face bonded to a 65nm Samsung image signal processor die and connected with W based TSV. The CIS die is fabricated on a 65nm CMOS process with 5 levels of interconnect as shown below, courtesy Chipworks.


ON Semi (Aptina)

In early 2015 On Semiconductor (Aptina) introduced its first stacked CMOS sensor the AR 1335 with 1.1µm pixels. It resulted in a smaller die footprint, higher pixel performance and better power consumption compared to their traditional monolithic non-stacked designs. They announced that it would be introduced in commercial products in late 2015. [link]


In late 215 Olympus announced the OL 20150702-1 a new 3D stacked 16MP CMOS image sensor [link]

For all the latest on Advanced IC Packaging, stay linked to IFTLE…


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One thought on “IFTLE 303 Sony Introduces Ziptronix DBI Technology in Samsung Galaxy S7

  1. ArethaRegalado8

    A file on Science, Technology, Design and Mathematics (STEM) from the Georgetown College Fixate Education as well as the Labor force forecasts 51% of STEM professions will certainly be computer occupations by 2018.


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