ByÂ Dr. Phil Garrou, Contributing Editor
Continuing our look at advanced packaging activity at the 2016 SEMICON Taiwan. This week, letâ€™s look at some interesting presentations on fan-out packaging.
Amkor â€“ Fan Out Solutions for Today and Tomorrow
Ron Huemoeller of Amkor addressed the status and future of fan out solutions. Amkor expects 2B fan out packages to be shipped this year.
Traditional WLFO applications and drivers are shown below.
Huemoeller reports that advanced Fan Out offers the following value proposition:
– reduced Z height and form factorÂ Â Â Â Â Â Â Â Â Â – enhanced signal integrity
– superior impedance matchingÂ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â – optimized power distribution
– improved thermal performance/junction temp
– ability to address multi die heterogeneous integration (i.e. SiP)
Traditional fan-out is reportedly gaining momentum in mobile market, i.e. RFIC, CODEC and PMIC
The table below shows their assessment of Amkor Advanced fan-out (SWIFT) vs FC CSP solutions.
They see advanced FO (i.e SWIFT and TSMCâ€™s InFO) being used in mobile applications such as
– Apps processorÂ Â Â Â Â Â Â Â Â Â Â Â Â Â – Baseband (logic + memory)
– power managementÂ Â Â Â – display driver SiPs
Right now they claim that traditional fan out has cost parity with FC CSP at 0.5mm die size.
K&S â€“ Equipment Selection for Fan-Out Process Flows
Strothmann of K&S detailed considerations to make when determining equipment for fan-out process flows.
- Past and current FOWLP is typically the Infineon eWLB variety but also can be Motorola RCP or Deca versions.
â€“ Lower I/O count devices
â€“ Mostly single die, some multi-die and a few die with passives
â€“ applications include Baseband, Power Management, RF, Analog, Bluetooth
- High Density FOWLP is expanding rapidly
â€“ Competing technologies in an unsettled market space
â€“ High density I/O capable
â€“ Application Processors, Memory, Multi-die Si Partitioning, Heterogeneous Integration
- Wafer vs Panel formats are also being examined
Strothmann notes the following FOWLP process flows in HVM today:
- Face Down, Die First: Typical Infineon licensed eWLB process, highest volume
- Face Up, Die First: Similar to flow used by TSMC and others, HVM potential
- Face Down, Die Last: Similar to Amkorâ€™s SWIFT or SLIM process
- Accuracy and UPH are Key Metrics for equipment selection in all flows
- Face down typically has the highest position shift but also has the highest UPH (lowest cost)
- Face up die placement accuracy can be improved with application of heat and force to lock die position
- RDL first allows for high accuracy due to metallurgy and die position being locked prior to reconstitution
FOWLP manufacturing today is primarily driven by a round 300mm format.
Panel format requires new processes and equipment to be developed
â€“ Panel size has not been set as an industry standard
â€“ Maximum panel size appears to be 650x650mm but many potential smaller sizes
â€“ Difficult for equipment suppliers to prepare
â€“ Immediate TAM is quite low due to die volume per panel
- Panel lines require significant loading for full utilization
- Larger package size is required to drive panel volume (SiP, IoT?)
- Adoption of mainstream panel processing remains a few years out
Strothmann suggests the following equipment selection criteria by process flow:
Yamada â€“ Wafer Molding for Fan-out Packages
Katsuyama-san of Yamada discussed wafer molding systems for fan-out packaging. Yamada has been around since 1953 working on standard lead frame packaging.
Their fan-out assembly process flow giving 5 sided protection is shown below. This is achieved by cutting grooves into the wafer isolating the components and backfilling them with molding compound as shown below:
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