Insights From Leading Edge

IFTLE 315: IMEC Leads at IEEE 3DIC 2016

By Dr. Phil Garrou, Contributing Editor

The 7th annual IEEE 3DIC Conference took place in SF a few weeks ago chaired by Paul Franzon of NC State and Bob Patti of Tezzaron. Without question, IMEC led all participants with several key papers at the conference. This week, IFTLE will look at IMEC contributions.

In their paper “Continuity and Reliability Assessment of a scalable 3 x 50μm and 2 x 40μm via-middle TSV Modules” IMEC describes a scalable via-middle module process, featuring an ALD oxide liner, a thermal ALD WN barrier and an electroless NiB platable seed. The module has been downscaled from 3μm to 2μm diameter TSVs. Both the front side to back side TSV continuity as well as the TSV reliability were found to be satisfactory.

When increasing the aspect ratio of the TSV from 10:1 to 17:1 and even 20:1 (for 3 x 50μm and 2 x 40μm respectively), the use of a conventional PVD barrier and seed reaches its conformality limits, as very thick layers need to be deposited in order to assure a continuous film at the bottom of the TSV. For this reason, an advanced and scalable 3 x 50μm TSV metallization scheme was developed and further scaled down to 2 x 40μm diameter/depth TSVs.

IMEC vias middle process flow is shown below.



The oxide liner is deposited in an ALD oxide system . 100% conformality is obtained over the entire TSV depth for 2 x 40μm TSV structures. The 17nm thermal ALD WN barrier is deposited followed by a 100nm electroless NiB seed . Both layers exhibit highly conformal deposition. The TSV copper electrofill is done on an ECD system. Void free filling is obtained for these 2 x 40μm TSVs placed at pitch of 5μm.

The device wafers are temporary bonded to a Si carrier wafer, using Brewer Science Zonebond process. Device wafer thinning is done by mechanical grinding, rough followed by fine grinding, to provide polished surfaces. The mechanical grinding is stopped before the first Cu TSVs are reached, thus leaving a silicon layer between the wafer backside and the tip of the TSVs. A wet process based on HF/HNO3 isotropically etches a few microns of Si, followed by an additional wet TMAH step, selective to the liner oxide, to reveal the TSV bottoms. Cu of the TSV remains encapsulated in the oxide liner. The back side passivation layer is processed on the revealed via bottoms. A low temperature nitride layer is deposited on the wafer backside, and a thick resist layer planarizes the whole surface. Blanket etch back of the layer without photolithography, to expose all TSVs while a thin resist layer remains on the field. The passivation layer together with the oxide liner are etched away in a dry etch process selective to the barrier metal. Finally, the resist is stripped.

Then back side RDL is integrated with a semi-additive process. TiW/Copper barrier and seed deposition, is followed by copper plating.

The liner/barrier integrity is verified by using the controlled I-V method The TSVs are tested in both copper confined (accumulation) and copper-driven (depletion) mode to check the quality of the oxide liner and WN barrier combination. The IVCTRL test indicates excellent barrier/liner reliability of the 2 x 40μm TSV.

In the IMEC paper “Die to wafer 3D stacking for below 10um pitch micro-bumps” reports on the process flow for embedded bumps for below 10um pitch micro-bumps. A process is introduced to fabricate Sn micro-bumps with zero undercut . Revealing bumps and planarization was done by CMP and surface planer. Initial TCB stacking showed well aligned bumps for 5um pitch daisy chains, good mechanical strength of bonded chips and IMC formation between Sn and bottom Cu pads. Calculations show that replacing Cu with Co and Ni will result in less material consumption which is interesting for sub 10um pitch micro-bumps.

In their embedded micro-bumps approach, micro-bumps are embedded in either organic or inorganic dielectric materials. As shown below UBM is processed in a damascene type approach and solder is embedded in a non-cured polymer or WLUF (wafer level underfill). Since a damascene process is used for UBM, spacing between them can be reduced. For 5um pitch, 1um spacing is used. Selection of solder diameter is based on alignment capability of TCB tool.

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It was found that at temperatures below 120oC, Cu/Sn IMC grows faster than Co/Sn or Ni/Sn IMC while at higher temperatures close to melting temperature of Sn (233oC) Co/Sn and Ni/Sn will grow faster.

The figure below shows plated Sn micro-bumps in 5um pitch and 40um pitch regions before seed etch.

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For die to wafer stacking an advanced high precision thermocompression bonding tool from Besi with alignment accuracy close to 1um was used. Total profile is around 10s with interface temperature of 250oC and force around 10-15kg. In order to prevent Cu or Co pads from oxidation during bonding, passivation layers such as SAM, NiB and immersion Au were used.

In their paper “Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects” IMEC reports that by taking into account the described alignment tolerances, via last diameters of 1μm enable 2μm pitch TSV interconnection densities.

When looking at dielectric bonding with via last TSV connections. Two wafers are finished with a very smooth, low-topography dielectric layer. The wafers are cleaned and the surfaces are activated by plasma processes. The wafers are subsequently aligned with high precision and brought into contact, resulting in a spontaneous room temperature wafer-to-wafer bonding. After annealing the bond between the wafers becomes permanent. The top wafer can then be thinned and backside via-last TSV contacts can be created to connect electrically to both the top and bottom wafer. The integration scheme is shown below.


The structure has 1μm diameter TSV on a 2 μm pitch. On top of the FEOL stack, 300mm top and bottom wafers have 1 damascene metal layer, called MET1T in the top wafer and MET1B in the landing or bottom wafer. Both wafers are finalized with a planarized SiO2 and a SiCN bonding layer. A SiCN bonding layer is preferred over SiO2 or SiON for its higher bonding strength. The top wafer is aligned to the bottom wafer and bonded at low temperature with high accuracy to the bottom wafer.

The bonding processing is completed by the post-bonding annealing process of 2 hours at 350°C to strengthen the bonded dielectric interface. After aligned bonding of the wafers, the top wafer is thinned to 5μm Si. The thinning process is a combination of wafer grinding, Si CMP and Si dry etch.

The wafer-to-wafer interconnects are realized with 1μm diameter TSVs, defined by through-5μm Si alignment on a high accuracy scanner. The smoothness of the Si surface is critical to enable the alignment. The TSVs are aligned to the corresponding landing pad.

In their final paper IMEC discusses “High-Density and Low-Leakage Novel Embedded 3D MIM capacitor on Si Interposer”. In this work they present a technique to fabricate embedded 3D MIM capacitor on Si interposer showing capacitance densities as high as 96 nF/mm2 and low leakage current of 1.5 pA/nF, while having a breakdown voltage of 10.5 V and > 10 years lifetime (T50%@1V,100 °C = 5.18e16 s).

The process flow is shown below.

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The list of investigated 3D MIM capacitor is shown in Table below.

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One thought on “IFTLE 315: IMEC Leads at IEEE 3DIC 2016

  1. Dr. Dev Gupta

    what is this SURFACE PLANER used by IMEC to reveal the plated Sn 2.5 um dia 5 um tall bumps ?

    ( referred to in the Text above :

    ” In the IMEC paper “Die to wafer 3D stacking for below 10um pitch micro-bumps” reports on the process flow for embedded bumps for below 10um pitch micro-bumps. A process is introduced to fabricate Sn micro-bumps with zero undercut . Revealing bumps and planarization was done by CMP and surface planer. .. )

    Is it a Tool / Process scalable to HVM ?


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