By Dr. Phil Garrou, Contributing Editor
The 13th 3D ASIP conference was held this year under the umbrella of IMAPS. This year’s meeting was chaired by Alan Huffman (Micross), Mark Scannell (CEA Leti) and Mitsumasa Koyanagi (Tohoku Univ) . I remained on board to help with the program organization and to transition the conference to IMAPS.
We’ll first take a look at the “Advances in Fan-out Packaging” course by Beth Keser of Qualcomm (see recent changes below) and next week begin with plenary lectures provided by Tetsuo Nomoto of Sony, Jean Michailos of ST Micro, Bill Chen of ASE and Subu Iyer of UCLA and then other key presentations.
Advances in Fan-out Packaging
Who better to teach the fan-out packaging course than the co-inventor of RCP while at Freescale. 20 years ago Beth was coating BCB wafers for Ted Tessier at Motorola, today she is the go to person for fan out packaging in the world. For those keeping track of such things, reports are that Beth has just become Director of Packaging at iCDG at Intel in Munich. This is the mobile business they bought from Infineon a few years ago that designs devices for mobile phones. You’ll remember them as the inventors of eWLB fan out packaging!
I won’t give away too much of her course since many of you have not yet seen the live presentation, which I recommend you all do to gain a complete understanding of what this technology is all about.
Lets start by offering up the IFTLE comment that I have used many times “ALL PACKAGES ARE FAN OUT EXCEPT FAN IN WLP” meaning lead frame packages, BGAs ect are all fan out.
By now we are all used to the FO-WLP process flow developed for the Infineon eWLB as shown below. With the proliferation of reconstituted, mold compound based FO-WLP, such processes have become known as face down, chips first.
Reconstituted Fan-out has really taken off recently as it has been developed for multi-die , i.e SiP applications and PoP (package-on-package) applications. It has also developed capabilities to achieve much higher densities in both face down and face up process flows. For PoP applications Keser point out that it:
– eliminates warpage and co-planarity issues since there is no substrate
– offers PoP height reduction
– eliminates stress on the die from bump interconnect (maybe but there is still stress – see InFO X-sect below)
Second generation products have been coming out in rapid progression but Keser cautions that only the InFO is currently available. – Xilinx / SPIL “SLIT” [IFTLE 215]
I will not go over all of these, but have given you links back to previous discussions in IFTLE
Of interest continues to be the upcoming ASE merger with SPIL and their announced investment to scale up the DECA FO-WLP technology [IFTLE 292].
I have commented in IFTLE 292 that DECA and InFO appear to be very similar technologies by polishing the surface during pillar expose step to produce a very flat surface for the RDL fabrication. Keser reports that TSMC is in production with 5/5 (L/S). Many of the speakers are showing InFO cross sections taken from analysis of the Apple A10 (TSMC has still not published process flow or cross section) I have included it below for those readers who have not seen it yet. This is a PoP package with memory on the top (side by side to thin the package down) and the processor below. Note the overall bow in the structure!
In short, “Fan-out packaging” is certainly expanding its technology capabilities and appears to be capable of taking significant package market share in the future.
For all the latest on Advanced Packaging, stay linked to IFTLE…