ByÂ Dr. Phil Garrou, Contributing Editor
Ma to Amkor
This week, I can announce that Dr. Mike Ma, with 23 years in the microelectronics industry, has moved from SPIL to Amkor as Taiwan Country Manager. Mike served as Vice President of Corporate R&D and Spokesperson at SPIL. Mike holds M.S. in Materials Engineering from Northeastern Univ and PhD in Material Science and Engineering from North Carolina State Univ.
Itâ€™s great to see someone who has maintained his keen interest and knowledge in technology attain such a lofty position. Many of you might remember Mike during his earlier days at UMC.
We all know that when consolidation occurs like the ASE â€“ SPIL merger (I know legally this is not being called a merger, but you also know IFTLE always calls a spade a spade) savings are achieved by staff reduction, especially at the higher levels â€“ redundancy they call it. In this case IFTLE is confident that my friends at ASE have made a major mistake letting Mike leave. IFTLE message to Amkor â€“ good pick up!
CMOS Imaging at 3D ASIPÂ
This yearâ€™s 3D ASIP put a special emphasis on CMOS image sensing.
It was the fall of 2007 when Toshiba first announced the commercialization of TSV in a CMOS image sensor (CIS). [see IFTLE 89 â€śAdvances in CMOS Image Sensingâ€ť]
In 2012 Sony announced that it was separating the pixel section (containing the back-illuminated structure pixels) from chips containing the circuit section for signal processing, and oxide bonding the layers and then connecting them with TSV. [see IFTLE 172 â€śSony TSV Stacked CMOS Image Sensors Finally Arrive in 2013â€ť]
Earlier this year [see IFTLE 303 â€śSony Introduces Ziptronix DBI Technology in Samsung Galaxy S7â€ť] a Chipworks teardown of the Samsung Galaxy S7 revealed the first use of the Ziptronix (now Tessera) Direct Bond interconnect (DBI) technology rather than prior oxide â€“oxide bonding with subsequent TSVs connecting through the oxide interface (In most circles this is referred to as â€śHYBRID BONDINGâ€ť and does not require TSV.
So it seems only fitting that this years 3D ASIP image sensing plenary presentation was by Tetsuo Nomoto, Sr General Mgr of Sonyâ€™s mobile imaging systems business. Sony sees several key applications for CMOS image sensor technology:
Nomoto indicates that the next generation will include stacked DRAM chips to achieve â€ś 5X faster scan out and storage data, improve distortion and reduce 1/F bandwidthâ€ť and then incorporating a DSP into the stack to 3 Layered modules with customized staked DRAM will be shown at the next IEEE ISSCC.
The audience really perked up when Nomoto indicated that Sony believes such technologies will be instrumental to furthering robotics and robotic manufacturing.
During the Tessera presentation by Paul Enquist, they described the new â€śhybrid bonding process as follows:
Since Sony is currently in production with 6um pitch and Tessera is currently capable of 1.6um pitch in demonstration vehicles, they feel they are close to pixel level interconnect technology.
Yole reports that back side stacked and back side stacked hybrid technology will take over ~ 60% of the marked by 2021.
Roc Blumenthal described SMICs CMOS image sensor capabilities.
Credit where credit is due
Lastly, that great cross section of the TSMC InFO package that I used in IFTLE 218 (shown below) inadvertently had the source cropped off on insertion into the blog. Full credit should go to Prismark consultants and Bingamton Univ. for this great tear down and cross section. Further details can be found in Prismarkâ€™s Semiconductor and Packaging Report Q3 2016.
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