ByÂ Dr. Phil Garrou, Contributing Editor
The annual IMAPS Device Packaging Workshop was held at its usual location outside Scottsdale AZ in early March. I noticed at this years meeting among the > 600 attendees were lots of new young faces who had no clue where this meeting came from.
Keeping the Historical Record Straight on IMAPS DPC
Since IFTLE is very picky when it comes to keeping the historical record straight, I just wanted to take a few seconds to remind the readership that this meeting was the brain child of Dr. Andy Strandjord who was both a colleague, in our days developing BCB at Dow Chemical, and the Tech VP of IMAPS at the time. In the early 2000â€™s there were several IMAPS workshops taking place on related thin film packaging topics like MCMs (now called system in package, SiP), bumping and the newly developed wafer level chip scale packaging (Fan in WLPs). Andy pulled them all together into tracks and initiated the Device packaging â€śworkshopâ€ť which is really a conference complete with extensive exhibitions, but with no requirement to write a full paper for submission. The first one was held in 2005 and was an immediate success. Next to the fall IMAPS meeting that IFTLE calls the â€śNationalâ€ť this is the 2nd largest IMAPS packaging focused meeting in the US and after the national and IEEE ECTC is the 3rd largest packaging meeting in the US period. Ted Tessier followed Andy as General Chair for a few years and I was chair in 2010 and 2011. Since then, Chairs have rotated out of the technical committee. Now back to this years conference.
I had heard rumors that there was a startup company doing FOWLP which was MIL qualified. Ends up this company is Aurora Semiconductor which spun out of DRAPER Labs in early 2016 by buying the St Petersburg FL facility. They indeed are DOD cleared, ITAR registered, ISO 9001 and are a DMEA Trusted Foundry Program member and accredited supplier.
IMAPS DPC was the first public presentation that I had seen from them, and is worthy of a closer look.
They have branded their technology 4DHSiP.
- Patented and licensed MCM approach
- Compatible with COTs (commercial off-the-shelf) components
- Chips first technology; FOWLP (Fan Out Wafer Level Package),
Similar to traditional eWLB technology chips are placed face down and overmolded into a wafer. The chips are then interconnected with RDL. These layers are then stacked and connected with through mold vias (TMV). They claim:
- 4 total layers of interconnect (7 topside and 7 bottom)
- Controlled Impedance Transmission lines
- Power/Gnd Bus; Multiple Power Domains
- Signal line Shielding for crosstalk isolation
They have developed several techniques including metallic â€śfinsâ€ť and â€śbridgesâ€ť to conduct heat away. Thermal control appears to be a work in progress.
Santosh Kumar of Yole Developpement gave a new forecast for TSV applications as shown below. They project the market to increase to $7.2B by 2021. 3D memory stacks will grow at the highest CAGR â€“ 48%. By 2021 MEMS & Sensors will become the biggest contributor to TSV application revenues.
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Thanks for the kind remarks. One correction. We have a 14 total interconnect layers (7 topside and 7 bottom)