ByÂ Dr. Phil Garrou, Contributing Editor
On the eve of the formal ECTC presentations, the conference held a panel session pitting wafer processing vs panel processing for the low cost production of â€śhigh densityâ€ť fan out WLP.
â€śIn the left corner representing wafer processing are TSMCâ€™s Doug Yu and Naniumâ€™s (Amkorâ€™s) Stefan Krohnert and in the right corner representing panel processing are Decaâ€™s Tim Olsen and IZM Fraunhofferâ€™s Rolf Aschenbrenner â€¦the referee for this match, representing user groups, is Qualcommâ€™s Steve Bezukâ€¦â€¦Letâ€™s get ready to rumbleâ€¦â€ť
Basically the question is: if and when will panel processing tools be fully developed and capable of manufacturing and testing fine L&S (i.e 2um) fan out packages produced in yields similar to silicon wafer lines. If/when this happens, how will silicon foundries counter such results.
Letâ€™s look at some of the key points made by the above parties during this hour plus discussion.
– [Yu] InFO leverages his companies core business â€“ i.e Si wafer processing
– [Krohnert] capital for FOWLP is already depreciated whereas there are no panel level processing in place so new capital will have to be expended on newly developed equipment.
– [Yu] Inspection of wafers is a well known process whereas panel inspection has to be developed
– [Yu] technology must be face down so you can package chips of different heights (polish) Face up panel tech cannot do this. â€¦also passives cannot be thinned like chips can be.
– [krohnert] â€ś..a fully loaded high yield wafer line might be cheaper than a partially loaded low yield panel lineâ€ť he went on to explain that if panel processes FOWLP only reached required yields for low-medium I/O devices there are other ways to manufacture such packages and the remaining â€śsweet spotâ€ť panel business may not be enough to fill panel lines.
– [Yu] landed a solid right to the jaw of his opponents when asked about what the silicon foundry response will be if indeed panel processing is developed and is yielding fine L&S. His response was that TSMC is part of the 450mm development team and although the equipment already developed and purchased by TSMC does not look like it will be processing leading edge node wafers any time soon, such tools and processes could easily be applied for 1-2um features. â€śThis would be low hanging fruit for such tools and processes.â€ť Yu then indicated that a possible plan is to make such a move when they feel the panel processing is ready. He cautioned, though, that this will produce a major oversupply of capacity.
– [Bezuk] the main volume for WLFO is currently for 3-5mm pkgs
– [Bezuk] InFO is currently the thinnest package you can buy today
– [Bezuk] equipment for panels is being developed but having problems like shedding particles during startup which is affecting yield
– [Bezuk] simple FOWLP like codec chips use a single layer of RDL, if multi layer RDL is required FOWLP becomes too costly
– [Bezuk] materials costs for both technologies are ~ 50% of the total.
– [Aschenbrenner] panel level processing shows a sweet spot for small-medium I/O devices
– [Olsen] projects a 30% cost advantage for large panel processing
– [Olsen] working with ASE on 300mm round today and panels in the future
– [Aschenbrenner] agreed that panel processing cost reduction will only be achieved when yields are close to the same as for wafers
– [Aschenbrenner] panels appear to need class 100 clean area to achieve yield on fine lines
– [Olsen] agreed that panel equipment is taking a long time to â€śget cleanâ€ť
IFTLE concludes that panel processing is still about the â€śpromiseâ€ť of lower costs. As such it certainly is worthwhile to do the work to find out if this can be put in place.
The major new news item from this panel was certainly TSMC bringing up the potential use of 450mm wafer equipment which would continue to leverage their core business/technologies, if and when it is economically required. Was this shared insight or a clever bluff?
Bar Cohen term
As a point of clarification, Dr. Avi Bar Cohens term of President of the IEEE Electronics Packaging Soc. (EPS) will begin Jan 2018.
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