Insights From Leading Edge

IFTLE 344 ECTC 4: Reliability Studies of 2.5/3DIC – Cisco, Infineon, Siliconware

By Dr. Phil Garrou, Contributing Editor

Continuing our look at presentations from ECTC 2017.

Cisco – Challenges of 2.5/3D

Li Li of Cisco gave a nice presentation concerning “Reliability Challenges in 2.5D and 3D Integration”

Compared with traditional 2D IC packaging, the emerging 2.5D and 3D IC integration involves several new elements in design, manufacturing and supply chain processes. These new elements include:

cisco 1


Let’s focus on one area that Li discusses that has for the most part gone under the radar since it is usually not addressed by back end practitioners – gettering. For further info on this topic IFTLE refers you to the work of Koyanagi and c0- workers at Tohoku Univ who have studied the impact of copper contamination on memory retention.

The devices formed from the thinned silicon wafer are more easily affected by metal impurity contamination and crystal defects. Because the Intrinsic Gettering (IG) region and the Extrinsic Gettering (EG) layer in the silicon substrate for gettering metallic contaminants are removed during the wafer-thinning process for the 3D IC fabrication. Potential Cu contamination from Cu TSVs is another concern that can further degrade the device reliability if the barrier for the Cu TSV is not designed and fabricated correctly.

Fig. 2 shows schematically the effect of IG layer and the potential risk of metal (Cu, Au, etc.) contaminants diffusing into the active region and cause device degradation.

cisco 2

Intel has reported Cu contamination from die backside causing high pin leakage after Unbiased Highly Accelerated Stress Testing and High Temperature Storage testing. To prevent Cu contamination from backside, an Ar ion implantation for Cu gettering and a SiN barrier was proposed.

Infineon & Nanyang Univ – Reliability of Copper TSV

Infineon and Nanyang reported on the “Reliability Evaluation of Cu TSV Barrier and Dielectric Liner by Electrical Characterization and Physical Failure Analysis”

The integrity of Ti barrier and SiO2 dielectric liner were evaluated via electrical characterization after being subjected to different stress tests such as high temperature storage, temperature cycling and electrical biasing to detect barrier and dielectric liner degradation in a the structure.

TC -65/150 °C up to 2000 cycles was performed on the structures to study the extent of barrier degradation by thermomechanical stress induced by TC. After electrical biasing, an increase in the inversion capacitance was observed in the C-V curve indicating Cu ions presence in the dielectric liner. It is suggested that the cracks formed after TC stress may have propagated within the Ti barrier. This can eventually lead to the drift of Cu ions into the dielectric liner under a sufficiently high E-field which acts as an external driving force for Cu ions to drift through the degraded barrier and cracks.

Siliconware – Warpage in 2.5D Modules

Siliconware described their “Warpage Study of Large 2.5D IC Chip Module”

SPIL lists four processes for 2.5D IC modules: Chip on Chip, Chip on Substrate, Chip on Wafer first (CoW-first), and Chip on Wafer Last (CoW-last). In this study, CoW-last was studied. CoW_last means the die are stacked on interposer wafer after the interposer is fully processed including frond side u-bump and backside via revealing (BVR), backside re-distribution layer (RDL) and C4 or Cu pillar bumping.

They found that for some specific designs, the area of multiple top dies are smaller than interposer, which produces empty area on interposer. This makes for unbalanced chip module stress and worsens chip module warpage.

Therefore, they propose a dummy die (DAF) structure(s) to fill up empty area on interposer. In this study, two dies are attached on interposer, as shown in the fig below. The thickness is the same as top die thickness.

spil 1

Underfill and molding compound

They found that a method for warpage improvement is to decrease the underfill volume by the design of lower bump/cu pillar height. Generally, high bump height provides the tolerance for warpage compensation because of more solder volume, and also enhance bump stiffness by low modulus underfill.

Assuming there is no reliability effects to low bump height, the underfill during cooling process acts a buffer material for stress releasing, but induces higher chip module warpage. From experimental results, when UF volume reduces 31%, the warpage between chip module and substrate can be reduce 10% at room and high temperature. “To decrease the volume of high CTE underfill really can improve the chip module warpage”. IFTLE reads this as meaning don’t make the bump/copper pillar higher than necessary to achieve the required reliability or it will negatively affect the warpage.

In terms of molding compound, the module with molding compound successfully negates the effects of CTE mismatch and leads to warpage reduction of 87% at high temperature.

For all the latest in Advanced Packaging, stay linked to IFTLE…


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