Insights From Leading Edge

IFTLE 353 Updating CMOS Image Sensor Technology

By Dr. Phil Garrou, Contributing Editor

A few weeks ago, we covered the Sony announcement of the Xperia XZ1, which features a 19MP Exmor RS camera with 960fps video capture and reportedly is fabricated as a stacked 3 layer CIS with DRAM. [see IFTLE 346 “Sony Introduces Stacked Image Sensor with DRAM in Xperia XZ phones]

This technology was first disclosed at IEEE IEM in 2016 as their “Cu2Cu Hybrid Bonding” [link] and discussed in IFTLE coverage of last falls 3D ASIP Conference [see IFTLE 319 “ …3D ASIP Part 2: Image Sensing – Sony, Tessera, SMIC”]

Those of us that have been following 3DIC for the past decade recognize this as the Ziptronix “DBI process” which they licensed to Sony a few years ago. It is now quite clear that the literature is generically calling this technology “hybrid bonding” since the bonding occurs to a surface containing both copper and oxide. Hybrid bonding does not have TSVs since it simultaneously connects the two substrates physically and electrically.

They depict there process flow as follows

Sony 1

The trench and via are made at the BEOL top layer of each wafer. Then, barrier metal and Cu seed are formed by PVD. Cu is plated up and annealed at the appropriate temperature. Excess Cu is removed by CMP to reveal the Cu connection pads and oxide dielectric. After face-to-face bonding, the wafer stack is annealed. As illustrated in their figure 4, the upper Cu pad and lower Cu pad are connected by Cu diffusion and grain growth, and the upper dielectric and lower dielectric are connected by dehydration-condensation reaction. They report that it is important to remove any voids from the Cu pad bonding interface during the post-ECD annealing.

Samsung CIS now include Stacked DRAM too

According to new reports [link], Samsung has developed and will begin mass production in November 2017 of a similar mobile camera sensor capable of 1,000 frames per second (FPS). Reports are that the camera contains a stacked 3 layer image sensor, with the layers made up of the sensor itself, logic chip, plus a DRAM chip that can temporarily store data.

While we are at it, let’s take a look at the advances covered at the recent Int Image Sensor Wkshp held in Hiroshima this past May.


Venezia of Omnivision described their “1.0um pixel improvements with hybrid bond stacking technology” discussing their Gen2, 1.0um CMOS image-sensor technology featuring hybrid bonding stacking.

Their first generation, stacked chip technology used oxide-oxide bonding and TSV to bond and electrically connect the sensor and logic wafers, respectively. “With stacking technology, the logic circuitry is placed under the array, resulting in an overall smaller chip size than is possible with standard BSI-CIS; where the circuit is located on the same wafer. Stacking also allows for sensor-only processes that improve CIS performance which could have negative impacts on circuit performance in a BSI-only process.”

The gen 2 technology uses hybrid bonding “where wafers-to-wafer bonding occurs at both the oxide and metal interfaces, and water-to-wafer interconnection is made at the top metal bonding pad. This architecture offers a better interconnect pitch and more flexible interconnect placement than the previous Gen1 approach. For instance, bonding can occur closer to the array edge, or even within the array.” The resulting chip size is 10% smaller using HB technology for the Gen2 1.0um, 16MP product.

fig 2



Hseih of TSMC gave a joint paper with Qualcomm on “A 3D Stacked Programmable Image Processing Engine in a 40nm Logic Process with a Detector Array in a 45nm CMOS Image Sensor Technologies”

They designed & fabricated a RICA (Reconfigurable Instruction Cell Array) ASIC wafer stacked with a pixel arrays wafer of 8MP, 1.1 um pitch BSI image sensor test vehicle. This device used “the 3D stacking technologies of a 45nm CIS process and a 40nm logic process at TSMC”.


Kagawa of Sony discussed “Novel Stacked CMOS Image Sensor with Advanced Cu2Cu Hybrid Bonding” further detailing their Cu2Cu hybrid bonding technology.

They describe the positive attribute of not having to create TSVs in their devices as follows “Making TSVs needs special fabrication equipment, such as deep Si etcher and high coverage metal/dielectric deposition tool. In addition to the fabrication problems, there are device problems. In particular,

the keep-out-zone (KOZ) strongly affects device specifications and circuit design. On the other hand, hybrid bonding does not have such problems. It can basically be fabricated by the conventional back-end-of-line (BEOL) process, and special equipment is never needed….Moreover, the Cu connection pad is located on top of the BEOL layer, and it never interferes with the MOS-FET during the fabrication process. It enables enormous circuit design flexibility and further chip size reduction can easily be achieved.”

Reliability tests were carried out under voltage and temperature stressed conditions. Predicted lifetime was estimated from Black’s equation as over 10 years. Extremely low leakage current and good TDDB reportedly indicate that the Cu connections are well isolated by the dielectric. They fabricated a stacked back-illuminated CMOS image sensor with “22.5 megapixel 1/2.6 size CIS featuring a 1.0μm unit pixel size and an ISP…” using their Cu2Cu hybrid bonding process.


Ray Fontaine of TechInsights in his “Survey of Enabling Technologies in Successful Consumer Digital Imaging Products” detailed the technologies responsible for the remarkable advances in mobile phone camera performance over the last decade.

He notes that “Two-die stacks, comprising a back-illuminated CIS and mixed-signal image signal processor (ISP), have emerged as the dominant configuration for leading smartphone camera chips” and adds that “The recent manufacturing trend for back-illuminated CIS chips in a stacked configuration seems to have stabilized at the 90/65 nm process generation “ as shown in the fig below.

Techinsights 1

He notes that Sony’s current leadership position in the industry is due to the fact that they were the first to bring stacked CIS chips to market, by implementing homogenous wafer-to-wafer bonding (oxide bonding) with TSVs in 2013 and Cu-to-Cu hybrid bonding, (also known as Cu2Cu bonding or DBI), in 2016. OmniVision’s first observed stacked chips, fabricated with foundry partner XMC in 2015, used a ‘butted’ TSV structure in which a single, wide TSV contacted both a CIS and ISP pad structure. OmniVision later adopted a unified TSV structure for its 1.0 μm pixel generation PureCelPlus-S chips, fabricated by foundry partner TSMC. The observed Samsung stacked chips in production also feature a butted TSV structure, but instead use a W-based TSV window liner for vertical interconnect. These are shown below.

techinsights 2

For all the latest on advanced packaging, stay linked to IFTLE…


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