ByÂ Dr. Phil Garrou, Contributing Editor
Continuing our look at 2017 SEMICON Taiwan.
John Hunt of ASE discussed his thoughts on â€śFan Out Packaging â€“ Simple to Complexâ€ť.
An interesting slide was his chronology of wafer Level (WL) packaging sine the adoption of bumping and RDL (the advent of Taiwan licensing the FCT technologies).
Hunt divides fan out (FO) categories into low density and high density options:
- Low Density fan out
– Less than 500-600 I/O
– L/S > 8Âµm
- High Density fan out
– Greater than 500-600 I/O
– L/S < 8Âµm
Early applications for low density FO include baseband and Rf transceivers. New opportunities include:
Early high density fan out opportunities include PoP and SiP
New Opportunities include:
– APU + memory
– GPU + memory
– Network applications
Note the GPU and Network apps begin to intrude into the space carved out by Silicon 2.5D. Such a product is described below:
Hunt showed the following ASE fan out package platform:
David Fang, CTO of Powertech discussed PTI panel level processing developments.
– Packaging for more than Moore modules is usually larger than 10x10mm and thus panel level processing provides 3-5X the efficiency of wafer level even at 300mm.
– They have found that the initial investment per module is 30-40% higher for panel level fan out modules than for fan in WLP.
Continuing challenges for panel processing include:
– No worldwide standards
– Tool and accessory readiness
– Process difficulties, i.e. panel warpage, chip shift, fine line patterning
An interesting slide details their thoughts on panel equipment selection based on technology from the Wafer, LCD and PWB industries.
Powertech fan out solutions are shown below.
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