Insights From Leading Edge

IFTLE 362 Broadcom Continues Consolidation; IMAPS 2017 Part 3

By Dr. Phil Garrou, Contributing Editor

Before we get back to the IMAPS 2017 conference, a few important items:

Consolidation – and the beat goes on

We have talked a lot about consolidation and why it is happening. [see IFTLE 255 “Consolidation continues …” and IFTLE 241 “Simply Obeying the Laws of Economics” ]

On November 6th Broadcom announced its intention to buy its rival, Qualcomm, for ~ $130B, including debt. If successful, it would be the largest deal in the history of the technology acquisitions. Following the consolidation trail, NXP acquired Freescale and Qualcomm is trying to acquire NXP and Broadcom is trying to acquire Qualcomm. Certainly a sequence that no one could have predicted a few years ago. If Broadcom successfully acquires Qualcomm, the combined group would become the world’s third-largest chipmaker, behind Intel and Samsung. If they combine, with no divestments, Qualcomm and Broadcom would control between 50%-60% of the market for Wi-Fi chips and 27% of radio-frequency chips for mobile devices.

The Economist offered the following table listing mega mergers (consummated and in process) [link]

economist 1

The Economist also offers the comment that “with Qualcomm’s pending purchase of NXP and Broadcom’s of Brocade, what looks at first glance like a merger between two giants is actually a four-sided deal. It would be difficult to unite so many different divisions and business units all at once” It certainly will be interesting to see what happens here!

Continuing our look at IMAPS 2017

InFO like FOWLP from ASM Pacific & partners

John Lau representing ASM coauthored the presentation “Fan out Wafer Level Packaging of Large Chips with Multiple Redistribution Layers” with a long list of co-workers. The design is a chips first face up process looking a lot like the TSMC InFO. The detailed descriptions of the processing are much appreciated. The overall process flow is shown below.

asm 1


As is the case for InFO the key processing sequence is plating up the contact pads on the wafer (30um), molding the wafer and hen grinding back the mold cmpd to expose the copper pads much like you would a TSV. Their mold compound is Nagase R4507 a liquid EMC with 85% filler content and an average filler particle size of 8um.

Subsequent processing of the RDL layers is shown below. The smallest L/S features on the bottom RDL layer is 5/5.



From this groups 2nd paper “Characterization of fan-out WLP” we learn that

– die attach accuracy and pitch compensation are the key issues that need to be controlled for accuracy in the RDL process

– die tilt is an important factor that affects the contact pad reveal so the die bonder should be optimized to control leveling

– molding concerns include die shift, warpage and voids. Mold cmpd choice will affect warpage results.

Namics & Hitachi Chemical

The presentation “Development of Liquid Compression Molding (LCM) Materials for Low Warpage” by Namics and Hitachi Chemical detailed the properties required for a low warpage LCM. They were able to substantially reduce LCM warpage by using aliphatic, flexible epoxy resins with low modulus and low cross link density.

Hitachi Chemical

Hitachi Chemical also detailed their studies on “Highly Reliable Cu Wiring Layer for 1/1um L/S using newly Designed Insulation Barrier Film.”

It is generally agreed upon that organic substrates fabricated by the semi additive plating process is limited to 8um L/S . To achieve finer interconnect pitch required by future FOWLP Hitachi Chem has studied trench wiring to create such high density structures. This sequence is typically laser ablation of the trenches in the dielectric, copper plating and subsequent planarization by CMP. Barrier metal is required to minimize copper migration so the seed layer for plating is generally 50nm of Ti followed by 100nm of sputtered Cu. The processes are compared below. For reliable HAST testing of 2/2 L/S they have found that covering exposed Cu with a Ni barrier layer is required.

Hitachi chem 1

They have also examined chemically amplified, negative tone, photosensitive dielectrics to achieve below 2/2 L/S. This processing includes the use of an insulation barrier film which shows low moisture absorption, low anionic impurities and high hydrolysis resistance. Using this combination they were able to achieve 1/1 L/S.

hitachi chem 2

For all the latest in advanced packaging, stay linked to IFTLE…


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