By Dr. Phil Garrou, Contributing Editor
OSRAM licenses m-transfer printing from X-Celeprint
IFTLE has discussed m-transfer printing for several years, first with Semprius [ see IFTLE 203 “Apple Acquires LuxVue µ-assembly Technology” ] and then at licensee X-Celeprint [see IFTLE 354 “The Case for µLED Displays”]
We have seen Teledyne using the technology in several DARPA programs and have heard rumors of the technology being used to develop mLED displays.
It now appears that a major player in word wide LED component marketplace has significant interest in the technology because OSRAM now reports that they have entered into a technology and patent licensing agreement with X-Celeprint for their m-transfer printing technology (link)
Exactly how will OSRAM use this technology in their LED products?? We’ll be keeping an eye out and report back to our readers…Heterogeneous Integration Roadmap Update at IMAPS DPC
Starting this week we will begin going over some of the presentations at the IMAPS Device Packaging Conf held every year outside Phoenix, AZ. At one of the keynote presentations Raja Swaminathan of Intel discussed his work on the Bill Chen Heterogeneous Integration Roadmap.
If you read this blog regularly you have probably picked up on the fact that IFTLE has little tolerance for bad nomenclature and/or redundant nomenclature. So, let’s consider the term “heterogeneous Integration” what this means is basically combining (i.e integrating) things that are not the same (i.e. heterogeneous)…i.e. a DRAM memory module is not heterogeneous integration (but would be homogeneous integration) . So is this something new ?? In the 1990s we called them multichip modules. Today that is also called a SiP. Too many terms meaning nearly the same thing for my liking.
But…given that the community has appeared to latch onto this catch phrase lets look at what the roadmap committee is doing about the naming.
Swaminathan makes the point that on package integration is more compact, low power and higher band width than off package connections (see below).
In order to improve on the meaningless terms 2.5D, 2.1D etc they are proposing that we consider these as 2D enhanced architectures as side by side active silicon interconnected at high densities using either organic or silicon based interposers.
So, TSMC’s CoWoS would be 2DS with TSV, ASEs FoCoS would be 2DO chips last and Intel’s EMIB would be 2DS without TSV.
Technologies are compared I terms of density below:
Swaminathan concludes with a slide showing on of the main themes of IFTLE for the past decade “Packaging technologies will become more wafer-fab like.”
For all the latest in advanced packaging, stay linked to IFTLE…
its getting sillier every year isn’t it as newbies try to make their mark by inventing ever more awkward terms for old & established concepts, putting old wine in new bottles ! What only matters is driving down the cost of dense / high bandwidth off – chip integration by advanced packaging ( e.g. SiP ) so we can afford to put AI inference engines even in high volume IoT type edge devices