ByÂ Dr. Phil Garrou, Contributing Editor
TSMC Introduces WoW Technology
At the TSMC Technology Symposium in Santa Clara, the company discussed their new Wafer-on-Wafer (WOW) silicon wafer stacking technology for the 7 and 5nm nodes. The â€śnewâ€ť technology connects chips on two silicon wafers reportedly using 10um TSV.Â Those of us who have been following 3DIC for over a decade recognize this as W2W 3DIC. Even the name isnâ€™t new, since Fujitsu introduced their version of WoW technology in 2010 which we discussed way back in in IFTLE 181.
TSMC first teased us with this potential technology back in 2014 at the IEEE IEDM.
The TSMC technology stacks and interconnects die while still part of the full silicon wafers vs their previous 2.5D technology CoWoS that uses silicon interposers. The advantage is obviously that this tech connects all die on two wafers in one process step. In terms of performance, direct 3D stacking has always been known as the highest performance lowest latency solution.
As we have known for a decade at least, there are several issues with W2W technology: (1) yield – bad die on wafer 1 will be connected to good die on wafer 2 resulting in a bad stack. This precludes this technology from being a viable solution for silicon that doesnâ€™t already offer high wafer yields. Ideally, TSMC reports that chip yields should be 90% or higher to use TSMCâ€™s Wafer-on-Wafer technology.Â (2) quite obviously this technology is most relevant for low-power silicon, where heat is less of an issue and (3) Also importantly, readers of IFTLE know that this solution works best for chips that are identical like memory stacking, but not for ships of different sizes and different I/O configurations which would require redistribution (RDL) before alignment and stacking is possible, thus increasing cost.
So far, TSMC has reportedly achieved â€ś2-layer stacks, in which two silicon layers that are mirror images of each other (for perfect alignment), sandwich bonding layers, through which pins for the upper layer pass through.â€ť
Since TSMC currently manufactures graphics cards for both AMD and Nvidia and there are some predicting that we will see stacked GPUs from the WoW technology. â€śThere wonâ€™t be latency problems between the connected GPUs as the wafer has the ability to let the GPUs communicate quickly, meaning we could see dual-GPU graphics cards based on current GPUs like the Polaris and Pascal GPUs from AMD and NVIDIA, respectively.â€ť [link]
Certainly they wouldnâ€™t be hyping the technology if there werenâ€™t real customers urging them to move forward with it. It will be interesting to see if they give a more complete description of WoW at the IEEE ECTC in a few weeks. If so be sure that IFTLE will get you the details.
What about designing these complicated structures ??
Cadence Teams with TSMC for full WoW Design Flow
Cadence has announced that its full suite of Cadence digital, signoff and custom/analog IC design tools, along with advanced IC packaging design solutions, support the new TSMC Wafer-on-Wafer (WoW) stacking technology. [link]
Cadence announced a new WoW reference flow to complement their other TSMC integration solutions ( InFO and CoWoS). They described the following design flows, tools and methodologies that will enable TSMC customers to manage the top-level connectivity and verification of their chip integration solutions as part of the overall design process as follows:
- Innovusâ„˘Â Implementation System: Supports single database top-die including front/back-side routing and backside-through-silicon-via (BTSV) support, creating connections between multiple dice
- Quantusâ„˘Â Extraction Solution: Supports back-side routing layers, sub-circuit replacement for BTSV and die-to-die interface coupling capacitance extraction, enabling electrical analysis between the dice
- Voltusâ„˘Â IC Power Integrity Solution: Provides die-level power map generation, enabling concurrent power analysis of multiple dice
- Tempusâ„˘Â Timing Signoff Solution: Provides multi-die static timing analysis (STA) support, enabling a checking of timing paths that cross multiple dice
- Physical Verification System (PVS): Offers design rule checking (DRC) and layout vs. schematic (LVS) for die with BTSV, interface alignment and connectivity checks, ensuring that the two dice connect properly
- VirtuosoÂ® Platform: Includes features for bump placement and alignment on top of the existing PDK via the Virtuoso Incremental Technology Database (ITDB), creating connections between multiple dice
- OrbitIOâ„˘Â interconnect designer: Provides interface connectivity, Â device flattening, port connectivity and configurable module definitions to manage top-level connectivity, enabling unified planning of die interconnect and alignment
- Sigrityâ„˘Â PowerSIÂ® 3D-EM Extraction Option: Offers electrical modeling of the combined die and interposer, validating that the power and ground distribution is sufficient for multiple dice
- Sigrity PowerDCâ„˘Â technology: Thermal analysis solution with interposer and die analysis capabilities that allow co-simulation with Voltus IC Power Integrity Solution, enabling inclusion of temperature into concurrent electromigration analysis of multiple dice
- SigrityÂ XcitePIâ„˘Â Extraction:Â Â Provides accurate interposer-level interconnect model extraction, enabling validation of high-speed signal propagation in the time and frequency domains
- SigrityÂ SystemSIâ„˘Â technology:Â Automatic construction of complete model-based interconnect topologies used to drive simultaneous switching noise (SSN/SSO) analysis for concise eye-diagram validation
For all the latest on Advanced Packaging, stay linked to IFTLEâ€¦
” TSMC first TEASED us with this potential technology back in 2014 at the IEEE IEDM ”
and the SHOW goes on ..
can you imagine the bond loads for whole wafer WoW if Cu Sn TC is still used ?
and no word on attempts to WoW by low load – low temp alternatives like HB ( Ziptronix / Invensas / Xperi )