Insights From Leading Edge

IFTLE 383 Global Foundries “Adv Packaging Trends in the Foundry Space”

By Dr. Phil Garrou, Contributing Editor

At the recent IMAPS Device Packaging Conference outside Phoenix Hamid Eslampour, CMOS BU Product Management, of GlobalFoundries (GF) discussed Advanced Packaging in the Foundry Space.

Eslampour indicated that todays networking, machine learning, and other high-end computing applications have created the need for architectures that allow for processing of massive amount of data located in nearby memory through communication with the CPU/ GPU with low latency, parallel processing, and high data rate.

To enable these solutions, advanced Si nodes with High-Speed-SERDES (HSS), enhanced HBM-PHY, and highly integrated package technologies are required. The packaging solutions they see providing the level of integration required include MCM, 2.5D, and 3D.

The challenge for foundries such as GF is to enable these solutions through co-design with the customer within a business model that provides the package design, technology integration, and OSAT manufacturing processes required.

High bandwidth and high performance computing technologies for silicon and packaging are shown below. Such high performance devices will require < 40um pitch copper pillar bumping and fine line interconnect (< 10/10 L/S).

fig 1-2

14nm designs are in customer development with 7nm and beyond designs in pathfinding.

fig 2-2

Current GF interposer capabilities are shown below and include 10um TSV on 40um pitch, up to 3 metal layers of 0.8um L/S interconnect:



GF has the following supply chain in place:

fig 3

Higher bandwidth trends drive higher number of HBM stacks, larger silicon interposers and larger power dissipation issues.

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