Insights From Leading Edge

IFTLE 388 2018 ECTC Part 3 TSMC & Samsung – Flexing their Muscle at ECTC

By Dr. Phil Garrou, Contributing Editor

General Observation

Sometimes, not always but sometimes, you can see a trend coming. When it comes to Adv Pkging, between 1995 and 2005 you could see the baton pass from the OEMS to the Assembly Houses (OSATS) as the papers we were all waiting for from IBM, NEC, Hitachi, Fujitsu, Toshiba, TI, Motorola, AT&T  started coming from Amkor, ASE, SPIL and StatsChipPac. IFTLE thinks we are in process of another baton pass from the assembly houses to the foundries and then maybe to the “newcomers”.

This ECTC saw TSMC and Samsung, usually minimal contributions or totally quiet participants, flexing their technical muscle and saying “see what we can do”. We also saw lots more attendance from the rich newcomers like Apple, Google and Amazon who are lurking and listening but not saying much of anything yet. IFTLE thinks this is not a one time occurrence, but rather the first signs of a broad baton pass where the front end players, who have seen that there are tech advances and monies to be made in the latest packaging solutions,  begin to take over the leading edge.

TSMC’s InFO has been a hot item for awhile now since it was incorporated into the Apple phone. The key breakthrough was the ability to planarize the surface and achieve 2um L/S (TSMC’s Doug Yu tells IFTLE this is grinding not CMP cause CMP would cost too much). At ECTC they told audiences they have broken the 1um barrier. Further, rumors were circulating that TSMC had been showing modules with high density interconnect approaching 0.5um L/S.

Another rumor making the rounds was that AMD was working with TSMC to directly bond SRAM stacks to CPUs…that’s right not 2.5D but full 3D mode. No substantiation on this one yet, but it sure is exciting to anticipate!

Let’s take a look at a few of the key papers by what I think will be the next generation giants in packaging. This week, we will look at several papers from TSMC. Next week, we will look at Samsung.


In the TSMC presentation High Performance, High Density RDL for Adv Packaging, the authors discussed how silicon interposer technology is limited to high-end applications due to its high fabrication cost and how fan-out wafer level packages with multi-layers high density RDL routings are emerging as a lower cost alternative to the 2.5D/3D silicon interposer in networking applications. They showed Table I to compare fine pitch, high density, advanced RDL technologies, namely BEOL, embedded Cu trace, and semi-additive process (SAP).

SAP has long been a main stream technology to form copper trace of packages in IC packaging applications. However, issues of degrading adhesion strength between copper line and dielectrics film and copper trace  undercut due to seed metal etching lead to reliability concerns as the L/S scales down to 3μm/3μm . Recently embedded Cu trace technology using UV laser to form fine pitch Cu traces was applied to organic substrates for lower cost considerations. Comparing with SAP technology, the embedded Cu trace technology not only provides a better adhesion between Cu trace and dielectrics material but also eliminates undercut and sidewall etching issues, which may worsen the transmission line loss at a high frequency.

They fabricated two layer Cu dual damascene RDLs as shown in the process below:

To validate the reliability integrity of two-layers embedded Cu dual damascene RDLs, they conducted the following tests: Thermal cycles (-65C ~ 150 C) 500 cycles, and unbiased HAST (130 C / 85% RH @33.5 PSI) 96 hours.

They successfully demonstrated a fine pitch, two-layers embedded Cu dual damascene RDLs with stacked vias on a 300 mm wafer using a single lithography dielectrics film. Each RDL layer composes of a sub-5 μm microvias and a 2μm/1μm line/ space escape routing using a Cu dual damascene process. The key aspects of the embedded Cu dual damascene RDLs such as structure, fabrication process steps, integration challenges, TV design and fabrication comparisons, reliability, R, C, and electrical transmission loss at high frequency were examined. We believe the Cu dual damascene RDL has the high potential to enable high density, high performance advanced packaging in future HPC and edge computing applications.

In their paper A Novel Submicron Polymer Re-distribution Layer Technology for Advanced InFO Packaging, TSMC addressed sub micron interconnect on their InFO packaging called InFO UHD (Ultra-High-Density).

TSMC offered that for multi-chip design architectures the key feature is to develop a high density route-ability technology across dies, which becomes an almost essential characteristic to serve this purpose. To achieve this, we need dimensional scalability of line-width and corresponding via size for  die-to-die interconnects to be deployed for more communications between chips. The fig below shows assessments as some examples of die-to die route-ability versus inter-chip RDL line-width (L) and RDL spacing (S). It is evident that miniaturization of these two RDL parameters do provide opportunities for more die-to-die communication paths on one interconnect layer if packaging products require, but it also implies less interconnect layers, which directly mean more cost competitiveness.

Another important factor is the area of the chip occupied by I/O pads The fig below shows the smaller and tighter pitch the better.

Some comments on the new technology include:

– It is preferable to manufacture with packaging-industry available tool sets instead of Cu/low-k in BEOL tools, to ensure competitiveness in cost to other techniques in current commercial market. Accordingly, for this technology, Cu RDL and Cu via are deployed by PVD barrier/seed with following electro-plating process, plus sufficient process support from etching, ash, and lithography to realize the designed fine line dimensional

architecture consisted of two RDL layers at least. All tool sets have been selected from current commercially available processing and metrological tools.

They demonstrated this technology with two-layer RDL of 0.8/0.8um L/S , and 1.5um vias.


When looking ahead to even finer dimensions for inter-chip packaging interconnect TSMC sees possible materials changes in areas such as RDL dielectric materials, molding materials, and lithographic photoresist materials. Low processing temp dielectric are suggested. Testing and metrology tools would also have to be upgraded to measure parameters with more accuracy.


In their paper Board level Reliability Investigation of FO-WLP Package TSMCexamines the effect of underfill on board level reliability.


A 15×15 mm2 package size InFO_PoP (fig below) was used as the test vehicle which consists of daisy chain test chip processed by 16nm wafer fabrication technology and three Cu RDL layers.

FO-WLP such as InFO has been rapidly adopted due to its excellent electrical performance due to its very short package level interconnection and its low cost. Since it exists as a very thin package without a package substrate to act as a stress buffer between the IC chip and system board, board level reliability performance of FO-WLP becomes challenge as products moving to large die size.

Thus board level underfill (UF) has been implemented in their Surface Mount assembly process (SMT) to prevent mechanical stress induced solder ball and redistribution layer (RDL) damage.  In general, the UF will help to reduce the mechanical stress to impact solder joint reliability. However, due to less sophistication of SMT UF process compared with FC UF process, special attention and optimization must be performed on such board level devices. Conditions are proposed to minimize reliability risk.

For all the latest on Advanced Packaging, stay inked to IFTLE…


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