Insights From Leading Edge

IFTLE 392 Chiplet Technology Discussed at DARPA ERI Kickoff

By Dr. Phil Garrou, Contributing Editor

IFTLE readers are well aware of the Electronic Resurgence Initiative (ERI) [ see “IFTLE 350 DARPA Electronics Resurgence Initiative: Going Beyond Moore’s Law”]

With “Moore’s Law,” which has guided the electronics industry for more than 50 years being challenged on both technical and economic grounds, the defense department is putting $1.5 billion into projects that could “radically alter how electronics are made.” [link]

Investments will support R&D in the areas of  Architectures, Design, and Materials and Integration. It is hoped that investments in these 3 thrust areas will lead the next wave of U.S. semiconductor advancement.

DARPA kicked off the initiative and revealed some of the winning proposals July 23-25 in San Francisco.


  • The goal of the Software Defined Hardware (SDH)program is to build runtime-reconfigurable hardware and software that enables near application-specific integrated circuit (ASIC) performance without sacrificing programmability for data-intensive algorithms.

Intel, NVIDIA, Qualcomm, Systems & Technology Research, Georgia Tech, Stanford Univ, U Michigan, U of Washington and Princeton Univ were selected for the SDH program

  • The goal of the Domain-specific System on Chip (DSSoC)program is to develop a heterogeneous SoC comprised of many cores that mix general-purpose processors, special-purpose processors, hardware accelerators, memory, and input/output (I/O).

IBM, Oak Ridge National Labs, Arizona St Univ and Stanford Univ were chosen for the DSSoC program


  • The goal of the Posh Open Source Hardware (POSH)program is to create an open source SoC design and verification ecosystem that will enable the cost effective design of ultra-complex SoCs.

Univ of California,San Diego, Northrop Grumman, Cadence, Xilinx, Synopsys, Univ of Southern California, Princeton Univ and Sandia National Labs were selected for the POSH program.

Materials & Integration:

  • The overall goal of the Three Dimensional Monolithic System-on-a-Chip (3DSoC)program is to develop 3D monolithic technology that will enable > 50X improvement in SoC digital performance at power. 3DSoC aims to drive research in process, design tools, and new compute architectures utilizing U.S. fabrication capabilities.

Georgia Tech, Stanford Univ, MIT and Skywater Technology Foundry were chosen for the 3DSoC program.

  • The goal of the Foundations Required for Novel Compute (FRANC)program is to define the foundations required for assessing and establishing the proof of principle for beyond von Neumann compute architectures.

HRL, Applied Materials, Ferric, UCLA, Univ of Minnesota and Univ of Illinois at Urbana-Champaign have been chosen for the FRANC program.

….and……….. CHIPS has now been included under the ERI umbrella

Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies (CHIPS)

IFTLE has had extensive discussions on the 2017 DARPA CHIPS program. [see IFTLE 323 “The New DARPA Program “CHIPS”…”].

The CHIPS program envisions an ecosystem of discrete modular, reusable IP blocks that can be assembled into a system using existing and emerging integration technologies. The program will develop the design tools and integration standards required to demonstrate modular integrated circuit (IC) designs that leverage the best of DoD and commercial designs and technologies.

Instead of building complex SoC on silicon the CHIPS concept sees future systems where each function is made separately (chiplets) and are then connected together on a larger slice of silicon by high-bandwidth interconnects. One of the challenges will be getting these chiplets to communicate properly and do so at a speed and energy cost that’s close to what they’d be if the system were all one piece of silicon. Interconnects using the standard will have to be capable of handling a lot of data without using much energy. It is estimated that it will have to cost less than 1 pico-joule to move a bit and be capable of moving 1 terabit per millimeter.

At the ERI kick-off, Intel CTO Mike Mayberry ,who is  VP and managing director of Intel Labs and holds responsibility for Intel’s global research efforts in computing and communications, revealed that Intel will provide their Advanced Interface Bus (AIB) technology, to program participants, royalty-free to help link chiplets together. AIB is a standard communications interface made for connecting different dies (chiplets) in the same package. Intel already uses AIB in 2.5-D packages such as the company’s Stratix 10 FPGA.

DARPAs Andreas Olofsson, manager of DARPA’s CHIPS program, reitterated the need for a standard communications interface. “… we need a plug-and-play standard……once we have that standard, you can imagine vendors offering a number of chiplets for sale.” The CHIPS program community is in the process of accepting the Intel AIB technology for this purpose.

USATF Jr Olympics

For my faithful readers of IFTLE, a quick update on the running career of grandaughter Hannah. In July of 2017, we discussed her new found ability to run on an elite level [link].

Well…she has continued this pursuit both with her Jr High and track club “Track Houston” and this year made the Jr Olympics. That’s right, I can now say that she is officially considered one of the fastest 13-14 yr old girls in the USA. She ran in the 4×400 and 4×800 races and medaled in the 4×800 as shown below.

For all the latest on advanced packaging, stay linked to IFTLE…



Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won’t automatically be posted to your social media accounts unless you select to share.

Leave a Reply

Your email address will not be published. Required fields are marked *