Insights From Leading Edge

IFTLE 395: And Then There Were 3; IC History for the Younger Generation

By Dr. Phil Garrou, Contributing Editor

The IC industry “poker championship” is down to the last table

The IC industry started out like a poker championship tournament. Hundreds of players, through the years, put up their entry fee to compete ( i.e. paying for their fabs) and the competition began. The most money was always made at the advanced nodes, i.e. the leading edge. There were winners and losers through the decades and we are finally down to the last table of players TSMC, Samsung, GlobalFoundries and Intel.

Last week, GlobalFoundries (GF) CEO Tom Caulfield announced that GF is putting its 7nm FinFET program on hold indefinitely and restructuring its research and development teams to support “…its enhanced portfolio initiatives”. The company will shift development resources to focus on its 14/12nm FinFET platform, “…delivering a range of innovative IP and features including RF, embedded memory, low power and more”. To support this transition, GF will initiate a ~ 5% global workforce reduction, however a significant number of top technologists will reportedly be redeployed on the 14/12nm FinFET programs [link].

Gary Patton, GF’s CTO added “…the number of players going into these advanced nodes has dropped significantly as result of the dramatic increasing costs to design in these leading-edge technologies… … then you look at the R&D cost …the R&D cost of these leading-edge nodes has been going up exponentially”

If you’re a long time reader of IFTLE, you already knew that!

On the heels of this announcement, AMD has announced that they will move all of its 7nm production on both CPUs and GPUs to TSMC [link]

Intel who launched their 14nm process in 2014 initially forecast their 10nm process for late 2016. Then that schedule slipped back to 2018. Now it’s slipped back into late 2019. These “Cannon Lake” delays are widely reported due to yield issues. [link]

Not good news for Intel when added to reports from Bloomberg that  Apple will start using their own chips in their products starting ~ 2020 (program code name “Kalamata”)[link]. Apple reportedly produces 5% of Intels income.

As we have been saying in IFTLE for many years now, the front end, node to node march called Moore’s Law is not dead, but certainly has been marginalized to the point where only a select few with major $$ and volume applications can play. For the rest of us, packaging is the new game in town and you better start learning the options that you have there.

A History Lesson for the Younger Crowd

Seeing all the global 20 somethings attending conferences like the ECTC is stimulating because it means our industry will continue to have a bright future. Talking to them reminds me that every now and then they need a history lesson so they can understand where all this came from.

I found the following schematic of the origins of our industry in a 1997 business week article. So if you have ever said “Who is Fairchild” and why does anyone care about them…here is the answer. As you can see some were winners and some were not.

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 394 DoDs ERI will Depend on Sky Water; Will Apple Get Caught in the Trade War?

By Dr. Phil Garrou, Contributing Editor

More on DARPAs Electronics Resurgence Initiative

In IFTLE 392, we discussed DARPA’s Electronics Resurgence Initiative (ERI), a $1.5B 5 year effort to remake the U.S. electronics industry. [link]

An interesting article appeared in this month’s IEEE Spectrum magazine entitled, “The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones” [link]

Among the 42 projects listed in the ERI, the “Revolutionizing Computing Systems through Dense and Fine-Grained Monolithic 3D Integration” project at $61MM is the largest on the list. Its goal is to use monolithic 3D integration to make chips made using decades-old fabrication processes competitive with chips made using today’s bleeding-edge technologies. The project is based on technology that allows carbon nanotube transistors and resistive RAM memory to be built on top of ordinary CMOS logic chips. It was developed by Max Shulaker, of MIT, and his colleagues at Stanford University. The program is being scaled up at SkyWater Technology Foundry in MN.

Over the next three years, Shulaker’s group at MIT will focus on developing a manufacturable process, and the Stanford group will create design tools that will help engineers take advantage of the increased performance that the stacking of CMOS, nanotube transistors, and RRAM offers. Skywater will develop and test a high-yield “process flow” that works in its foundry. So exactly who is SkyWater technologies ?

In March of 2017, Cypress Semiconductor sold its 200mm Fab 4 in Bloomington, Minnesota, to SkyWater Technology Foundry for $30 million [link].

Skywater announced that their intent was to operate the fab as a stand-alone USA specialized foundry. Skywater agreed to manufacture wafers for Cypress under a multi-year supply agreement while it tries to attract other foundry customers (similar to the IBM Global Foundry agreement of a few years ago). Cypress had operated the automotive-qualified fab since it acquired it from Control Data VTC in 1990. The fab reportedly has a clean room floor space of 80,000 square feet and was capable of 16,700 wafer starts per month. Cypress had about 450 employees at the Bloomington wafer fab in December 2015. ” SkyWater reports that it supports both low volume, fast turnaround processing and high volume production. It runs manufacturing processes from 0.35-micron down to 90nm.

The SkyWater facility maintained its “trusted site” accreditation allowing it to provide wafer fabrication, design, wafer test, and broker services to the US government as a trusted supplier. SkyWater announced its plans to expand engagements with the DoD [link]

According to Sky Water, they are now the only American-owned pure-play silicon foundry in the country as shown in the fig below.

The Sky Water technology roadmap is shown below.

Could Apple could find itself at the center of the US vs China trade war?

This from China’s Global Times [GT]  [link] “…. Why has the California-based company (Apple) enjoyed remarkable success in China, while some Chinese companies have experienced big losses amid a growing trade conflict with Washington …”

Apple recently reported financial results for its fiscal third quarter and sales to the greater China region gained 19 percent to $9.6 billion. GT contends the company’s better-than-expected quarterly result in China was a major reason for the surge in its shares. China serves as a key production and processing base for Apple. Many Chinese companies have been included in Apple’s production chain to provide parts and components or assembly work.

GT contends that the Apple success in the Chinese market “…may provoke nationalist sentiment if US President Donald Trump’s recently adopted protectionist measures hit Chinese companies hard”.

China is reportedly the most important overseas market for the Apple, leaving it exposed if Chinese people make it a target of anger and nationalist sentiment. China reportedly doesn’t want to close its doors to Apple despite the trade conflict, but GT warns “.. if the US company wants to earn good money in China, its needs to share its development dividends with the Chinese people..” and  “It is impractical and unreasonable to kick the company out of China, but if Apple wants to continue raking in enormous profits from the Chinese markets amid trade tensions, the company needs to do more to share the economic cake with local Chinese people”.

GT notes that “Apple’s contribution to job creation in China is notable, but the company enjoys most of the profits created from its Chinese business”. In the case of the iPhone, their statistics show Chinese processors only get 1.8 percent of the total profits created by the device.

For all the latest in advanced packaging, stay linked to IFTLE…

Readers –

We have received the following message from Bruce Gray CEO of TSI Semi challenging the information presented by Sky Water on their slides that I presented above.

“The information from Skywater included in this SST article …[IFTLE 394]…regarding TSI Semiconductors Corp. is completely inaccurate.   TSI Semiconductors Corp is 100% U.S. owned by U.S. citizens and not as the map by Skywater indicates.   The subsequent statement by Skywater that they are the only American owned, pure play Silicon foundry is therefore wrong as well.

TSI Semiconductors Corp is ITAR and Trusted foundry certified and has numerous customers that use our high quality and fast cycle time manufacturing for their critical projects.   TSI provides MEMS, Superconducting, and Photonics process development and manufacturing services, and, TSI serves the rapidly expanding medical device and analytical “lab on a chip” product markets also.

Importantly, TSI Semiconductors is certified to the new Automotive IATF-16949 manufacturing standard.  Our facility has 150,000 sq ft of clean room with a maximum capacity of 25,000 200mm wafers per month and lithography capability as small as 110nm.”

IFTLE looks forward to doing a blog on TSI in the near future…

IFTLE 393 Samsung Adv Pkging at ECTC: Emphasis on Warpage Control

By Dr. Phil Garrou, Contributing Editor

At the 2018 ECTC, Samsung presented several papers on their advanced packaging activities.

Samsung teamed with SUNY Binghamton to discuss “design Guidelines of 2.5D Package with Emphasis on Warpage Control and Thermal Management.” A 2.5D Package is composed of many material sets and in general its size is larger than conventional single chip packages. The CTE of substrate is a well-known factor to control warpage in a single die packages. However, the existence of another layer (interposer) makes the problem more complicated. Optimization of the material sets, which include lid, EMC, chip, Interposer and geometric factors, are essential.

From their modeling studies it is clear that substrate CTE is more influential than other criteria.

They developed the following guideline for warpage control and thermal management:

Area ratio of lid attach, lid thickness, EMC CTE and substrate CTE are major factors influencing for warpage. For thermal management, EMC coverage on top of the chip, (cooling) fan speed, and conductivity of TIM are the major factors that affect thermal resistance.

In their presentation on “Low Cost Si-less RDL Interposer Pkg for High Performance Computing Applications” In this presentation a concept for a Si-less redistribution layer is descried for server/HPC applications and warpage behavior, electrical performance and reliability of the RDL interposer package were evaluated.

Si-interposer have attracted attention for high end sever products due to  high electrical performance at low power consumption. The key barrier of Si-interposer adoption, utilizing TSV, is high manufacturing cost for large interposer sizes. They suggest a Si-less redistribution layer (RDL) interposer platform for high performance applications as a low cost package solution.

The table below compares 2.5D Si interposer technology to wafer level and panel level RDL interposers.

The fabrication process flow of RDL interposer package is classified into six main steps as summarized in the fig below.  RDL formation, multi-chip bonding on RDL, encapsulation, chip exposure, solder ball attachment, and interposer assembly on PCB. The most challenging aspect of the assembly is reportedly the warpage control of interposer packages, due to the large size and multichips.

Samsung clams that the RDL interposer package has the advantage of lower manufacturing cost over Si-interposer by replacing TSV with RDL. Their results showed that RDL interposer warpage is more controllable than Si-interposer at room and high temperature by the optimization of design, process condition and material selection. Their test structure, a RDL interposer package whose size is larger than 3000mm2 included four HBMs and one ASIC chip, was successfully fabricated and they determined that the electrical loss of RDL interposer was lower than Si interposer case. Mechanical simulation showed RDL interposer reduced joint stress by 34% compared to Si interposer. They predict that RDL interposer tech will become one of the most promising solutions for low cost and large size packages in the near future if “….fine patterning technology is developed below L/S 2/2um.

For all the latest in advanced packaging, stay linked to IFTLE…

IFTLE 392 Chiplet Technology Discussed at DARPA ERI Kickoff

By Dr. Phil Garrou, Contributing Editor

IFTLE readers are well aware of the Electronic Resurgence Initiative (ERI) [ see “IFTLE 350 DARPA Electronics Resurgence Initiative: Going Beyond Moore’s Law”]

With “Moore’s Law,” which has guided the electronics industry for more than 50 years being challenged on both technical and economic grounds, the defense department is putting $1.5 billion into projects that could “radically alter how electronics are made.” [link]

Investments will support R&D in the areas of  Architectures, Design, and Materials and Integration. It is hoped that investments in these 3 thrust areas will lead the next wave of U.S. semiconductor advancement.

DARPA kicked off the initiative and revealed some of the winning proposals July 23-25 in San Francisco.


  • The goal of the Software Defined Hardware (SDH)program is to build runtime-reconfigurable hardware and software that enables near application-specific integrated circuit (ASIC) performance without sacrificing programmability for data-intensive algorithms.

Intel, NVIDIA, Qualcomm, Systems & Technology Research, Georgia Tech, Stanford Univ, U Michigan, U of Washington and Princeton Univ were selected for the SDH program

  • The goal of the Domain-specific System on Chip (DSSoC)program is to develop a heterogeneous SoC comprised of many cores that mix general-purpose processors, special-purpose processors, hardware accelerators, memory, and input/output (I/O).

IBM, Oak Ridge National Labs, Arizona St Univ and Stanford Univ were chosen for the DSSoC program


  • The goal of the Posh Open Source Hardware (POSH)program is to create an open source SoC design and verification ecosystem that will enable the cost effective design of ultra-complex SoCs.

Univ of California,San Diego, Northrop Grumman, Cadence, Xilinx, Synopsys, Univ of Southern California, Princeton Univ and Sandia National Labs were selected for the POSH program.

Materials & Integration:

  • The overall goal of the Three Dimensional Monolithic System-on-a-Chip (3DSoC)program is to develop 3D monolithic technology that will enable > 50X improvement in SoC digital performance at power. 3DSoC aims to drive research in process, design tools, and new compute architectures utilizing U.S. fabrication capabilities.

Georgia Tech, Stanford Univ, MIT and Skywater Technology Foundry were chosen for the 3DSoC program.

  • The goal of the Foundations Required for Novel Compute (FRANC)program is to define the foundations required for assessing and establishing the proof of principle for beyond von Neumann compute architectures.

HRL, Applied Materials, Ferric, UCLA, Univ of Minnesota and Univ of Illinois at Urbana-Champaign have been chosen for the FRANC program.

….and……….. CHIPS has now been included under the ERI umbrella

Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies (CHIPS)

IFTLE has had extensive discussions on the 2017 DARPA CHIPS program. [see IFTLE 323 “The New DARPA Program “CHIPS”…”].

The CHIPS program envisions an ecosystem of discrete modular, reusable IP blocks that can be assembled into a system using existing and emerging integration technologies. The program will develop the design tools and integration standards required to demonstrate modular integrated circuit (IC) designs that leverage the best of DoD and commercial designs and technologies.

Instead of building complex SoC on silicon the CHIPS concept sees future systems where each function is made separately (chiplets) and are then connected together on a larger slice of silicon by high-bandwidth interconnects. One of the challenges will be getting these chiplets to communicate properly and do so at a speed and energy cost that’s close to what they’d be if the system were all one piece of silicon. Interconnects using the standard will have to be capable of handling a lot of data without using much energy. It is estimated that it will have to cost less than 1 pico-joule to move a bit and be capable of moving 1 terabit per millimeter.

At the ERI kick-off, Intel CTO Mike Mayberry ,who is  VP and managing director of Intel Labs and holds responsibility for Intel’s global research efforts in computing and communications, revealed that Intel will provide their Advanced Interface Bus (AIB) technology, to program participants, royalty-free to help link chiplets together. AIB is a standard communications interface made for connecting different dies (chiplets) in the same package. Intel already uses AIB in 2.5-D packages such as the company’s Stratix 10 FPGA.

DARPAs Andreas Olofsson, manager of DARPA’s CHIPS program, reitterated the need for a standard communications interface. “… we need a plug-and-play standard……once we have that standard, you can imagine vendors offering a number of chiplets for sale.” The CHIPS program community is in the process of accepting the Intel AIB technology for this purpose.

USATF Jr Olympics

For my faithful readers of IFTLE, a quick update on the running career of grandaughter Hannah. In July of 2017, we discussed her new found ability to run on an elite level [link].

Well…she has continued this pursuit both with her Jr High and track club “Track Houston” and this year made the Jr Olympics. That’s right, I can now say that she is officially considered one of the fastest 13-14 yr old girls in the USA. She ran in the 4×400 and 4×800 races and medaled in the 4×800 as shown below.

For all the latest on advanced packaging, stay linked to IFTLE…


IFTLE 391 DoD Worried About Access to State-of-the-art Packaging Technologies

By Dr. Phil Garrou, Contributing Editor

Continuing last week’s conversation about access to state-of-the-art packaging capabilities if you are not a large volume player, let’s look at the current concerns of the USG (US govt).

In the early years of the microelectronics industry the US Govt with its defense and communications requirements drove the electronics industry. In recent decades, however, commercial applications and high-volume production have dwarfed US Govt demand, resulting in commercial market forces driving the industry. Advanced packaging in the 1980s – 1990’s was driven by the integrated  device manufacturers (IDMs) in the US and Japan ( IBM, AT&T, TI, Motorola, DEC, HP, Hitachi, Fujitsu, Toshiba, NEC).

By the early 2000’s it had become clear that the demand for more and more I/O required a move to area array interconnection to replace the I/O limited Wire Bond technology that was in place. Up till then area array technology, exemplified most prominently by “bumping” was a technology only practiced by the mainframe computer companies. Starting ~ 2000  several of the evolving assembly houses in Taiwan and Korea like ASE, Amkor, Siliconware, STATSChipPAC (all located in Asia) licensed the US bumping and wafer level packaging technology of FCT (Flip Chip Technologies, Phoenix ,AZ) and Unitive Electronics (RTP, NC) and made such technology available worldwide. This technology was quickly adopted into portable consumer as well as computer products.

The massive commercial bumping capacity that was put in place in Taiwan and Korea delivered higher profit margins to these assembly companies separating them from those without such technology availability, and making US companies reliant on getting such technology from overseas. It also made it clear to these select assembly companies that “advanced” packaging was a higher profit margin packaging and assembly business that was worth their investment.

During the period 2000 – 2015 we slowly saw a year–to-year migration of the leadership in advanced packaging technologies moving from the afore mentioned IDM’s to these select major assembly houses in Asia.  This shift is best seen by analyzing the presentations at the IEEE Electronic Component Technology Conference (ECTC) which is the accepted world showcase for advanced packaging technologies. Ironically, the assembly houses, which were created to absorb the “packaging grunt work” the IDMs no longer wanted to do, discovered the potential financial advantage of developing the next generation advanced packaging solutions and ran with it.

We now appear to be in the process (2015–2020) of shifting leadership to the large global foundry houses like TSMC, Samsung and GlobalFoundries. Their ability to obtain finer geometry features using front end technologies, their comfort with processes like CMP and their comfort working in clean environments has put them in a position of strength for the latest high density packaging solutions.

Obtaining business with the Apple’s of the world now hinges on having both the best chip solution and the best packaging solution. Companies like TSMC saw this early on and have been investing heavily in developing the latest leading edge packaging solutions

Trusted Microelectronics Joint Working Group

In 2017 a diverse group of semiconductor industry, defense primes, DoD, and research institute professionals was assembled as a Joint Working Group to look into the future of microelectronics in the US and specifically how that future will impact the economic well-being and defense of our country. That list of participants is shown below:

Their findings included:

– there has been a migration of key supply chain elements particularly chip fabrication and packaging to overseas locations

simple access to the parts needed from the larger global electronics industry base has become a  large concern

The figure below was developed to show the tactical and strategic nature of the access issue.

When looking at emerging technologies they especially called out:

1. 3D / Heterogeneous Integration

2. Compound Semiconductor

3. Advanced Node CMOS

4. Other Novel Technologies: Advanced Digital, Analog Computing, Neuromorphic and Quantum

Access to Adv Node CMOS

The DoD requires access to state-of-the-art (deep node) CMOS for a number of current applications as well as R&D efforts for future systems. Advanced digital computation requirements benefit tremendously from state-of-the-art (SOTA) CMOS solutions.

SOTA CMOS fabs are very large and expensive with high volume commercial facilities costing over $10B. R&D expenses are also enormous. For this reason, there are only 4 companies left that offer SOTA CMOS: INTEL, GLOBALFOUNDRIES, Samsung and TSMC. All of these companies rely on the scale of high volume manufacturing to finance the capital and R&D requirements to maintain their competitiveness.

As a result of the enormous cost and complexity of the SOTA CMOS business, DoD access has become very difficult in recent years. There is a substantial difference in business model between commercial needs to produce very large volumes of a small mix of parts while DoD requires substantially fewer parts across a broad device mix. The NRE costs associated with SOTA design and fabrication make the high mix, low volume requirements difficult to attract commercial interest in servicing the DoD.

DoD has addressed this challenge in the past through its “Trusted Foundry” contract with IBM. This ended in 2015 with the sale of IBM Microelectronics to GlobalFoundries (GF), a foreign owned firm. The

In the long run, it is important for DoD to have assured access to secure SOTA CMOS from a variety of sources. Given the very different business models of the commercial world and DoD, this will be a challenging goal to achieve.

Access to 3D / Heterogeneous Integration technology

In terms of advanced packaging this study specifically called out  3D / heterogeneous integration technology and the assembly of microbumped flip chip dies onto interposer substrates and noted that :

“…..Therefore, the challenge for trusted heterogeneous integration technology is to stand up and maintain trusted 2.5D / 3D integration and assembly supply chain capabilities”

They concluded that :

There is grave concern today about the growing gap between commercial suppliers (many critical suppliers are offshore or owned by foreign entities) and defense needs. In the past, semiconductors and even software were created from a small number of large onshore vertically-integrated companies that had close ties and large business interests with the defense industries. The disaggregation of this industry into hundreds of international suppliers combined with commercial uses/volumes of microelectronics that far outstrip the DoD needs has created this alarming gap. This gap continues to grow.” 

“A National Strategy will need to encompass the entire lifecycle of DoD system needs (up to 50 year lifetimes and small volumes) and mesh that with the relative “mayflies” of the commercial world (< 2 years lifetimes and billions of devices…..The existence of China’s National Semiconductor Strategy cannot go unmentioned. They aim for total self-sufficiency and are investing heavily in their infrastructure. The US should not blindly emulate this approach but needs to develop its own unique strategy for ensuring long term access to secure components as well as enabling US economic vitality in this area. Creation of a practical US National Microelectronics Strategy will be a challenging multi-year process, requiring good insights into the future of the industry as well as intimate knowledge of the workings of the USG. The authors of this paper believe that this process should start now.”

Assured Supply for Microelectronics Manufacturing:Solicitation Number: W15QKN-18-X-02S7

In June 2018  the U.S. Army Emerging Technologies Contracting Center, on behalf of the Under Secretary of Defense for Res and Eng, issued a request for information (RFI) seeking information on business models and/or public-private partnerships (PPP) to provide long-term, economically-viable, assured sources to meet US commercial and government needs for state-of-the-art (SOTA) microelectronics design, fabrication, and packaging within the US domestic ecosystem. The U.S. Government (USG) is seeking inputs from the commercial microelectronics industry, industrial and standards groups, research and development contributors from government and industry, and states and regional governments, and private capital market players in this area. “This is a RFI not a Request for Proposal (RFP) or a promise to issue an RFP in the future”.

They define the problem as “The licit and illicit offshoring of intellectual property (IP), research and development (R&D), and production capabilities threaten the ability of U.S. companies to capitalize for the market-driving technologies of the future, opens critical infrastructure and data systems to attack, and degrades our national security. The current set of incentives offered by the USG can be better aligned to retain domestic capacity and technology leadership. The USG only represents less than 2% of the global commercial market for  microelectronics, and with current USG unique procurement policies, standards, and security requirements, industry lacks incentives to willingly and affordably meet the government microelectronics demands.”

Other nations will innovate faster, capture market share, and obtain the best technology at the expense of the U.S., impacting domestic innovation and the manufacturing base. The U.S. may lose the ability to realize the best ideas and capabilities across commercial and national security sectors, becoming dependent on competitor nations. A reliance on foreign made microelectronics with unreliable assurance and security could disrupt USG access to advanced technology critical to national security, and in general, devastate U.S. manufacturing, business, financial, and communications infrastructure.”

The goal of the information procurement is to develop a program to “…ensure the U.S. is recognized globally as the preferred source for superior microelectronics; delivering technology faster, more efficiently, and with the highest levels of assurance. …. Domestic foundries and packaging capabilities will support these activities, translating leading-edge R&D into new products. Assurance and security become competitive advantages for U.S. industry practiced at all stages of development and production ensuring the nation delivers reliable and superior microelectronics components, systems, and capabilities more quickly than other nations.”

The Government recognizes the need to proactively engage with industry to make such efforts successful . They report that they are executing a plan to provide semiconductor and microelectronics leadership now and into the future with a “whole-of-government effort”.  The U.S. Army Emerging Technologies Contracting Centeris requesting information on behalf of the USG on how to achieve the above outcomes most effectively.

Sources are encouraged to provide their ideas for the structure and sustainability of commercial business arrangements and/or PPPs necessary to deliver microelectronics manufacturing and leadership in a domestic ecosystem now and into the future. Sources are requested to respond to this RFI with a white paper.

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 390 Raytek – An Accessible Wafer Level Packaging Start-up in Taiwan

By Dr. Phil Garrou, Contributing Editor

While all readers of IFTLE know that advances in chip packaging have been proceeding at a rapid rate at the same time as front end IC advances are becoming harder and harder to achieve, access to these advanced technologies are difficult if you are not one of the large volume players. So, if you are a low volume supplier to the DoD or a custom supplier to smaller companies with low volume requirements you will have trouble finding someone willing and capable of doing business with you in advanced packaging and interconnect.   Note, I’m not talking about accessing 3DIC with TSV, I’m talking wafer level packaging including bumping, RDL, copper pillar bump etc. Try going to Amkor, ASE, TSMC or Global Foundries if you need a 100 wafer or 25 wafer order filled.

The response you get will be “No, thanks…nothing personal, you understand… it’s just a business decision.”

Now some of you may say “wait a minute…I know that Xilinx does 2.5D for FPGAs at TSMC and those are low volume products”…You are correct…but that’s for Xilinx…and the rest of you are not Xilinx.

Lets take a break from ECTC coverage to look at an under the radar advanced packaging option if your volumes don’t allow you to access the top tier foundries and assembly houses.

Raytek Semiconductor

Raytek Semiconductor was formed in April 2016 in Hsinchu Taiwan by packaging  veterans Johnson Tai  and Dyi Chung (DC) Hu to service customers’ needs specifically in wafer level packaging. Raytek is tooled for  both 300 and 200mm wafers. Beside silicon , their line can also process glass and  ceramic  wafers. Raytek also have a separate 150/100mm manufacture line to process GaN and other non silicon wafers.

Current clean room space is 1677 sq meters with phase 2 additional space of 1582 sq meters coming on line  as required. Process areas are class 100. Current wafer capacity is 12,000 wafers/mo.

Since setting up the company two years ago, they claim ca. 100 customers  products have been designed with a 100% passing rate after function evaluation and reliability test.

Raytek WLP services include:

– RDL: Cu RDL & Cu/Ni/Au RDL

– Bump: Cu Pillar Bump & Lead Free Bump

– WLCSP: Plated Bump

– WLCSP: Ball Drop (Q4/2018)

300mm Services:

– Cu/Ni/Au RDL, Thick Cu UBM/RDL

– Cu/Ni/Au RDL for Au or Cu wire bonding

– RDL L/S = 5/5um and Multi-layers RDL (up to 4PI/3Metal)

– Cu RDL for GaN wafers

-Low or high temperature cure dielectrics can be selected depending on requirements, 4-10um std.

-Applied in specialty memory , high power IC

– Bump ( Lead free bump, Cu pillar bump )

– Lead free solder and low alpha emission lead free solder can be plated

– Copper pillar pitch is 40µm, with max height 135um

-Applied in ASIC, Controller, Power, RFIC, High end memory devices (8GDDR4,HBM)

– One Stop Service

– Backside Grinding, Backside Metal, Dicing, Tape & Reel done in house

So, if you’re in need of these types of services check out Raytek.

So for all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 389 Samsung 2μm L/S Panel Level Packaging Technology Revealed at ECTC

By Dr. Phil Garrou, Contributing Editor

This week and next, IFTLE will take a look at the key Samsung presentations from the recent ECTC meeting in San Diego.

As we have said many times on IFTLE, fine pitch solutions is certainly an area where the major foundries have a packaging advantage over the OSATS. The Samsung Packaging Development Team presented a paper entitled “Fan Out Panel Level Package with Fine Pitch Pattern” discussing the technical challenges of fine pitch processing on a panel level process.

Samsung Panel Level Processing

Panel level package (PLP) is being examined because it appears to be the most cost-effective technology due to its large working area. Compared with 300mm wafer size, about 3 times number of units can be accommodated in Panel of 500 X 400 mm size. SEMCO (Samsung Electro-Mechanics) has developed a platform for FOPLP as shown in the fig below.  RDL technology enables the IO’s from semiconductors fanned out through RDL to PCB, while organic PCB is introduced as core structure in Fan-out area.

Many concerns remain regarding commercialization of Panel Level Packages related to process capabilities and yields. The most emphasized ones concern warpage and the generation of fine features. As we know, Fan out can be done RDL last or RDL first. As requirements of finer patterns are needed, RDL first process is seriously considered because fine patterns can be easily obtained on relatively flat carriers compared with molded wafers or panels. Samsung points out that currently patterns of about 10/10 um line and space has been successfully formed in chip first Fan-out package and 5/5 um of pattern is expected to happen in advanced Fan-out package, while 2/2 um of pattern required for die to die interconnection in such applications as 2.5D interposer drive the consideration of an RDL first processes solution.

In this study Samsung attempted to fabricate 2/2 L/S on glass and PWB panels of 415mm x 510mm size. The CTE of organic carrier composed of resin with glass was 8 ppm/C and the thickness was 0.6mm. The CTE of the glass carrier was also 8ppm/C and the thickness was 1.1mm. The Fig below compares organic carriers and glass carriers with regard to the extent of panel warpage.

The warpage of the glass panels was less than a quarter that of organic carrier. In addition, during the assembly process of large die with fine pitch micro bumps (typically 55um pitch) also requires very flat condition to avoid warpage caused non-wets or shorts.

Samsung feels that the concern that 2/2 um patterning on panels will be difficult may be due to the observed panel warpage and flatness. As the pattern pitch is decreased, available depth of focus (DOF) during lithography must be reduced, which requires very flat conditions. As the pattern pitch is reduced below 2/2 um, available DOF is decreased below 10um and toward about 5um level even though it depends on exposure equipment. Therefore, large panel warpage or high waviness on surface to be exposed may cause poor capability or yield with fine pitch.

Using the glass panels the Samsung group was able to do photolith and produce 2/2um L/S as shown in the fig below. A PBO dielectric was used to create 2 layers of 2/2 interconnect with 6um vias connecting them.

So a rigid carrier with high thickness or stiffness seems to be needed because multi layers on organic carrier resulted in the failure in exposing equipment (stepper) due to the high panel warpage. In case of glass carrier, about 5mm warpage was observed on the panel.  Even in that condition, the stepper table could hold the panel effectively under vacuum and there was no problem related with focusing the panel surface.

Another consideration regarding multi-layered panel was whether the pattern below passivation may affect the flatness of the passivation layer surface which consequently affects the fine pattern on it (i.e. is he surface planarized enough so that CMP or some other form or planarization aren’t needed between each layer of interconnect) . In the cross-sectioned image of 2/2 um pattern on second passivation layer shown below you can see the dip in the central area, which contained no sub layer features. Further study is needed to determine how much is flatness degradation due to lack of global planarization will induce failure in 2/2um pattern above.

Samsung also presented an excellent discussion on known good substrates.  In case of chip last RDL first process, the dies must be bonded to known good RDL. Therefore electrical test of the RDL carrier is a very important issue. One has to deal with the small bump pad size of about 20 – 25um diameter and the extremely large number of bumps (about 200K). A major issue is the probing of the interconnect. It is difficult because the electrical probe cannot be contacted on both side of all signal lines, but some must be checked by contacting on only one side of the signal lines. To check by only one side contact and decide if there is open or short, the capacitance of line or pattern must be measured exactly. Feasibility tests were done for one side contacted electrical test. The intentionally opened lines are well distinguished from the good signal lines as the line opened at the farthest position is differed by about 40% of measured values.

This is technology obviously still in R&D, but it is the strongest set of data that IFTLE has seen showing the possibility of manufacturing high density interconnect on large panel format…It certainly showed Samsung flexing it’s technical muscle !

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 388 2018 ECTC Part 3 TSMC & Samsung – Flexing their Muscle at ECTC

By Dr. Phil Garrou, Contributing Editor

General Observation

Sometimes, not always but sometimes, you can see a trend coming. When it comes to Adv Pkging, between 1995 and 2005 you could see the baton pass from the OEMS to the Assembly Houses (OSATS) as the papers we were all waiting for from IBM, NEC, Hitachi, Fujitsu, Toshiba, TI, Motorola, AT&T  started coming from Amkor, ASE, SPIL and StatsChipPac. IFTLE thinks we are in process of another baton pass from the assembly houses to the foundries and then maybe to the “newcomers”.

This ECTC saw TSMC and Samsung, usually minimal contributions or totally quiet participants, flexing their technical muscle and saying “see what we can do”. We also saw lots more attendance from the rich newcomers like Apple, Google and Amazon who are lurking and listening but not saying much of anything yet. IFTLE thinks this is not a one time occurrence, but rather the first signs of a broad baton pass where the front end players, who have seen that there are tech advances and monies to be made in the latest packaging solutions,  begin to take over the leading edge.

TSMC’s InFO has been a hot item for awhile now since it was incorporated into the Apple phone. The key breakthrough was the ability to planarize the surface and achieve 2um L/S (TSMC’s Doug Yu tells IFTLE this is grinding not CMP cause CMP would cost too much). At ECTC they told audiences they have broken the 1um barrier. Further, rumors were circulating that TSMC had been showing modules with high density interconnect approaching 0.5um L/S.

Another rumor making the rounds was that AMD was working with TSMC to directly bond SRAM stacks to CPUs…that’s right not 2.5D but full 3D mode. No substantiation on this one yet, but it sure is exciting to anticipate!

Let’s take a look at a few of the key papers by what I think will be the next generation giants in packaging. This week, we will look at several papers from TSMC. Next week, we will look at Samsung.


In the TSMC presentation High Performance, High Density RDL for Adv Packaging, the authors discussed how silicon interposer technology is limited to high-end applications due to its high fabrication cost and how fan-out wafer level packages with multi-layers high density RDL routings are emerging as a lower cost alternative to the 2.5D/3D silicon interposer in networking applications. They showed Table I to compare fine pitch, high density, advanced RDL technologies, namely BEOL, embedded Cu trace, and semi-additive process (SAP).

SAP has long been a main stream technology to form copper trace of packages in IC packaging applications. However, issues of degrading adhesion strength between copper line and dielectrics film and copper trace  undercut due to seed metal etching lead to reliability concerns as the L/S scales down to 3μm/3μm . Recently embedded Cu trace technology using UV laser to form fine pitch Cu traces was applied to organic substrates for lower cost considerations. Comparing with SAP technology, the embedded Cu trace technology not only provides a better adhesion between Cu trace and dielectrics material but also eliminates undercut and sidewall etching issues, which may worsen the transmission line loss at a high frequency.

They fabricated two layer Cu dual damascene RDLs as shown in the process below:

To validate the reliability integrity of two-layers embedded Cu dual damascene RDLs, they conducted the following tests: Thermal cycles (-65C ~ 150 C) 500 cycles, and unbiased HAST (130 C / 85% RH @33.5 PSI) 96 hours.

They successfully demonstrated a fine pitch, two-layers embedded Cu dual damascene RDLs with stacked vias on a 300 mm wafer using a single lithography dielectrics film. Each RDL layer composes of a sub-5 μm microvias and a 2μm/1μm line/ space escape routing using a Cu dual damascene process. The key aspects of the embedded Cu dual damascene RDLs such as structure, fabrication process steps, integration challenges, TV design and fabrication comparisons, reliability, R, C, and electrical transmission loss at high frequency were examined. We believe the Cu dual damascene RDL has the high potential to enable high density, high performance advanced packaging in future HPC and edge computing applications.

In their paper A Novel Submicron Polymer Re-distribution Layer Technology for Advanced InFO Packaging, TSMC addressed sub micron interconnect on their InFO packaging called InFO UHD (Ultra-High-Density).

TSMC offered that for multi-chip design architectures the key feature is to develop a high density route-ability technology across dies, which becomes an almost essential characteristic to serve this purpose. To achieve this, we need dimensional scalability of line-width and corresponding via size for  die-to-die interconnects to be deployed for more communications between chips. The fig below shows assessments as some examples of die-to die route-ability versus inter-chip RDL line-width (L) and RDL spacing (S). It is evident that miniaturization of these two RDL parameters do provide opportunities for more die-to-die communication paths on one interconnect layer if packaging products require, but it also implies less interconnect layers, which directly mean more cost competitiveness.

Another important factor is the area of the chip occupied by I/O pads The fig below shows the smaller and tighter pitch the better.

Some comments on the new technology include:

– It is preferable to manufacture with packaging-industry available tool sets instead of Cu/low-k in BEOL tools, to ensure competitiveness in cost to other techniques in current commercial market. Accordingly, for this technology, Cu RDL and Cu via are deployed by PVD barrier/seed with following electro-plating process, plus sufficient process support from etching, ash, and lithography to realize the designed fine line dimensional

architecture consisted of two RDL layers at least. All tool sets have been selected from current commercially available processing and metrological tools.

They demonstrated this technology with two-layer RDL of 0.8/0.8um L/S , and 1.5um vias.


When looking ahead to even finer dimensions for inter-chip packaging interconnect TSMC sees possible materials changes in areas such as RDL dielectric materials, molding materials, and lithographic photoresist materials. Low processing temp dielectric are suggested. Testing and metrology tools would also have to be upgraded to measure parameters with more accuracy.


In their paper Board level Reliability Investigation of FO-WLP Package TSMCexamines the effect of underfill on board level reliability.


A 15×15 mm2 package size InFO_PoP (fig below) was used as the test vehicle which consists of daisy chain test chip processed by 16nm wafer fabrication technology and three Cu RDL layers.

FO-WLP such as InFO has been rapidly adopted due to its excellent electrical performance due to its very short package level interconnection and its low cost. Since it exists as a very thin package without a package substrate to act as a stress buffer between the IC chip and system board, board level reliability performance of FO-WLP becomes challenge as products moving to large die size.

Thus board level underfill (UF) has been implemented in their Surface Mount assembly process (SMT) to prevent mechanical stress induced solder ball and redistribution layer (RDL) damage.  In general, the UF will help to reduce the mechanical stress to impact solder joint reliability. However, due to less sophistication of SMT UF process compared with FC UF process, special attention and optimization must be performed on such board level devices. Conditions are proposed to minimize reliability risk.

For all the latest on Advanced Packaging, stay inked to IFTLE…

IFTLE 387 Broadcom Looks to Advanced Packaging; Rumors from ECTC San Diego

By Dr. Phil Garrou, Contributing Editor

Boon Chye Ooi , Sr VP of Operations for Broadcom spoke at the IEEE ECTC luncheon addressing “Packaging advancements to enable artificial intelligence (AI), autonomous cars and wearables in the near future: cost and implications to supply chains.”

Broadcom’s Sam Karikalan, ECTC General Chair introduces Boon Chye Ooi , Sr VP of Operations for Broadcom

Ooi leads the global operations organization which is responsible for worldwide manufacturing including foundry and package engineering, outsourcing, procurement and logistics, planning and quality programs. Ooi indicated that he saw packaging as having played a vital role in enabling semiconductors to penetrate new application frontiers such as artificial intelligence (AI), autonomous cars and wearables, but for their ubiquitous deployment, the packaging community must make these technologies cost competitive and multi sourced.

He had 3 questions for the supply chain:

  1. Is the OSAT/Foundry willing to invest fab like yield tools?
  2. Will there be sufficient capacity and reliability of supply?
  3. How will cost excursions and miss-processing be handled by the infrastructure?

His call to action for the supply chain of 2022 included the following points:

  • Upgrade assembly yield management to Fab level
  • Develop u-bump probe and test technologies for improved yield
  • Develop substrates for low loss mm wave channels on large packages
  • Develop low cost thermal solutions to reduce system cost
  • Develop multiple suppliers for silicon content, packaging raw material, substrate and assembly

Specific technical challenges included the following:

  Desired Goal Issues
Data rate 112 Gbps · channel insertion loss and return loss

· crosstalk

· power integrity

Package Body size > 90 x 90mm · package warpage

· board level reliability

· socket cost and performance penalty

2.5D Integration More and larger dies · interposer reticle size

· assembly challenges

· more memory bandwidth

u-bump pitch < 30um · assembly challenges

· routing challenges


Power dissipation >500W · thermal interface materials

· heatsink solutions


Rumors from San Diego

With 1750 attendees present there were sure to be numerous rumors making the rounds at ECTC. In time some will clearly turn out to be true and some will not, but all of them are certainly interesting enough to consider.

One rumor I can confirm is that Rao Tummala, unquestioned “Father of Microelectronics Packaging”  will be retiring imminently. Tummala, now in his mid 70’s, has informed Ga Tech and his PRC that a successor should be located. He will be helping his replacement for a few years to ensure a smooth transition but he is looking forward to relaxing, spending more family time and playing more golf. It certainly will be interesting to see who Ga Tech finds to fill his shoes.

As I have detailed several times in IFTLE, BT (before Tummala) packaging was an after thought carried out by failed front end engineers. In 1989 Tummala, while still at IBM, joined Gene Rymaszewski editing the first Microelectronic Packaging Handbook categorizing this technology for the first time. In 1993 Tummala left IBM to set up an NSF PRC (packaging research enter) at Georgia Tech to explore and develop packaging concepts and, just as importantly, educate highly-interdisciplinary students in this concept. This NSF funding was supplemented by more than 50 U.S. companies and the State of Georgia. 20 new faculty were recruited with expertise in every electronics area. The 1st of a kind cleanroom pilot line for package, assembly and reliability was built at a cost of $47M. In the intervening years more than 400 PhD, 470 MS and 340 BS engineers all specializing in packaging have graduated from this program and populated the electronics companies around the world. In 1997 the Packaging handbook was rewritten in 3 volumes and more than 2000 pages. The chapter author list is a who’s who in the field of packaging. I am proud to have been part of that endeavor. Below is a photo we took in Slovenia together 21 years ago in 1997.

In 2001, Rao produced what I consider the first undergrad / grad packaging text “Fundamentals of Microsystem Packaging,” which has been used to teach electronics packaging in many of our universities. He and I co-wrote the chapter on wafer level packaging, a new concept at that time. My point in reciting all this is to simply backup my statement that these will be very large shoes to fill. It will be interesting to see who will fill them.

For all the latest in Advanced Packaging, stay linked to IFTLE…


IFTLE 386 IEEE EPS Awards at 2018 ECTC

By Dr. Phil Garrou, Contributing Editor

Memorial Day in the US means the start of the IEEE ECTC meeting, which is run by the IEEE EPS society (Electronic Packaging Society). This years 68th meeting was in San Diego and broke all records with an attendance of > 1750. There were 369 presentations in 36 oral sessions (6 in parallel) with authors from 28 countries.

The exhibition has been at capacity for several years with 106 exhibitors and reportedly 40+ on a wait list. IFTLE concludes that eventually this meeting must move to convention centers because it is becoming too large for hotel spaces available.

In this first blog on 2018 ECTC we will look at the EPS 2018 award winners.

The IEEE EPS Field Award

As we have discussed in the past the major packaging award in the world is the EPS “Field Award” meaning the top award in the “field.” This year’s winner is Bill Chen from ASE. The photo below shows IEEE President Jose Moura giving the award to Bill.

Dr. Bill Chen accepts EPS Field Award

Bill received his engineering education at University of London (B.Sc), Brown University (M.Sc) and Cornell University (PhD).  He joined IBM Corporation at Endicott New York in 1963. At  IBM  he  worked  in  a  broad  range  of  IBM microelectronic packaging products. He received IBM Division President Award for his leadership and innovation in Predictive Modelling on IBM products.    He was elected to the IBM Academy of Technology for his contributions to IBM Products and Packaging Technologies. He retired from IBM in 1997.  He joined the Institute of Materials Research and Engineering (IMRE) in Singapore, as Director of the Institute till 2001 when he joined ASE Group, where he holds the position of ASE Fellow and Senior Technical Advisor with responsibilities for guidance to technology strategic directions for ASE Group.

He is Senior Past President of the IEEE/CPMT Society. He is the Co-Chair of the ITRS Assembly and Packaging Roadmap Technical Working Group. He is a Fellow of IEEE and Fellow of ASME.  He has served as an Associate Editor  of ASME Journal of Electronic Packaging, and IEEE/CPMT Transactions.

EPS Electronics Manufacturing Technology Award

The 2018 IEEE EPS Electronics Manufacturing Technology Award was given to Douglas Yu of TSMC for “contributions to the development and high volume manufacturing of interposers and wafer level fan out packaging”. Dr. Yu received his B.S. degree in Physics and M.S. degree in Materials Science and Engineering both from National Tsing Hua University, and his Ph.D. in Materials Engineering from Georgia Institute of Technology. Dr. Yu was appointed TSMC’s Vice President in November 2016. Dr. Yu joined TSMC in 1994. He was previously Senior Director of the Integrated Interconnect & Packaging Division, where he led the development of interconnect technology for integrated circuits. Below we see Dr. Yu (L) accepting his award from EPS President Avi Bar Cohen.

Doug Yu receives Electronic Manuf Award

The IEEE EPS Outstanding Sustained Technical Achievement Award went to Professor Pradeep Lall of Auburn for “outstanding sustained contributions to the design reliability and prognostics for harsh environment electronic systems”.

The IEEE EPS Exception Technical Achievement Award went to three practitioners in the 2.5/3D technical space: Prof Mohannad Bakir of Georgia Tech; Prof Kuan-Neng Chen of National Chiao Tung Univ in Taiwan and Dr Katsuyuki Sukama of IBM.

All the awards were for “contributions to 2.5 and 3D IC heterogeneous integration, with focus on interconnect technologies.”

The IEEE EPS David Feldman Outstanding Contribution award went to EPS past president Jean Trewhella for “20 years of leadership consistently driving change collaboration and engagement in EPS and ECTC, including driving our society name change, sponsoring the heterogenous Integration roadmap and establishing the ECTC student reception.”

Newly elected Fellows included:

Kuan-Neng Chen – National Chiao Tung Univ , Taiwan
Klaus-Dieter Lang – Fraunhoffer IZM, Germany
Jinmin Qu – Northwestern Univ
Guo-Quan Lu – VPI
Saibal Mukhopadhyay – Georgia Tech
Stefan Grivet-Talocia – Politecnico de Turino, Italy

…and while we are talking awards.

Corning Presents First Annual ‘Corning Leadership in Glass Award’ at ECTC 2018

At the ECTC, Corning presented the first annual “Corning Leadership in Glass Award” to Proff Rao Tummala and his group at Ga Tech. The award recognized the technical paper “Design and Demonstration of Highly Miniaturized, Low Cost Panel-Level Glass Package for MEMS Sensors,” submitted by Georgia Tech at ECTC 2017 that best demonstrated the viability of glass for semiconductor packaging applications.

“We’re pleased to accept this very special award from Corning,” said Tummala. “We have long believed that the properties and fabrication of ultra-thin glass make it the best next generation material of choice for semiconductor and system package integration manufacturing processes after metal-based packaging since 1970s, ceramics since 1980s, organic laminates since 1990s and silicon since 2010. We’re proud that the research we’ve done in glass panel packaging in both chip-first and chip-last architectures, is gaining more and more acceptance.” Because of this special and unique nature of glass packaging, we converted our whole Center to glass packaging for high-bandwidth computing, 5G communications, power, mems and sensors and others.”

Dr. Venky Sundaram, Chintan Buch (student), and Prof. Rao Tummala (left to right) accept the inaugural ‘Corning Leadership in Glass Award’ at ECTC 2018.

For all the latest on advanced packaging, stay linked to IFTLE…