By Dr. Phil Garrou, Contributing Editor
Continuing our look at the IMAPS 3D ASIP Conference 2016.
Mike Kelly of Amkor updated their status on 2.5 and 3D multi die packaging.
High density solutions on 2.5D interposer technology are focused on data center, networking, HPC and military.
Amkors 2.5D production readiness:
– MEOL wafer thinning and backside processing
– 300mm TSV line in K4 … K5 starting Jan 2017
– SPC control
– automated wafer handling
– yield > 97.5 % (die level)
– production in K4 (85K parts built to date)
Yields > 98%
Comparison of Signal Routing for high density technologies:
SWIFT production readiness:
– internally qualified
– ready for small body high volume production in Q2 2017 in K5
– large body process in development
Routing capabilities are compared below: Slim > 3x SWIFT > 3X FC
Emilie Jolivet of Yole shared information on memory stacks. Their look at memory stack IP concludes that the area has been dominated by Samsung, Hynix, Micron/Elpida as you would expect.
UCLA CHIPS Program
We have previously discussed the Subu Iyer CHIPS program at UCLA [ see IFTLE 301 “Are Silicon Circuit Boards in our Future?”]
As described before, the plan here is to “disintegrate” (system partition) into functional blocks. These blocks would become a standardized IP library which would be available later as reusable IP. These chiplets (or dielets – the community has not decided what to call them) would then be recombined on a high density silicon fabric to fabricate the desired module. Iyer has calculated that these small (< 3 x 3mm) chiplets would require ~ 5um L/S to interconnect them. Lot of similarities to the current. In many ways this approach is similar to the CEA Leti chiplet activity and the DARPA CHIPS program which we shall look at soon.
When you think about temporary bonding you certainly think of Brewer Science who has been developing products for this technology area for over a decade.
Through the years they have developed products for several potential debonding schemes:
Their latest development is a two part system called “thermo+ cure” bonding where a thermoplastic layer (~ 2um) first encapsulates the device features followed by a curable layer (~60um; 150-200 °C). Debonding, occurs at the thermoplastic / cured layer interface as shown below. No part of the structure, after curing, can flow during backside processing.
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