By Dr. Phil Garrou, Contributing Editor
Now, at first glance you may be saying, “Why is IFTLE concerned with the Toshiba’s memory business? This is an advanced packaging blog!” But I hope most of you have learned IFTLE lesson #1 which is whatever effects chips, directly affects chip packaging. So with that in mind, the recent report by Reuters that Apple is looking into joining the Foxconn bid is very interesting. [link]
The sale of the Toshiba memory business is reportedly being driven by “…multi billion dollar writedowns at Toshiba’s US nuclear unit, Westinghouse” which has recently declared bankruptcy. The collapse of Westinghouse, once the key to Toshiba’s plans to diversify away from consumer electronics, has been hastened by nuclear power project delays in Georgia and South Carolina. Reports from Toshiba are that losses for the year may total > One trillion Yen [link]
To prevent total corporate bankruptcy, Toshiba put up its memory business for sale. Toshiba reportedly narrowed down its list of offers to bids from Broadcom, SK Hynix, Western Digital and Foxconn. According to the Reuters report, Apple was not part of the initial Foxconn bid. .
According to Reuters, Apple is considering taking a 20% stake (several billion dollars) in the Foxconn bid, Foxconn would take 30% and Toshiba would keep a partial holding so the business would remain under US and Japanese control. Reportedly “…Foxconn has been considered a national security risk (to Japan) due to its ties with China”.
This would fit with Apples stated goal of insuring a stable supply of key components. Apple has traditionally used Toshiba’s flash memory in its iPhones and iPads, especially after competitive issues with Samsung developed. Ownership of Toshiba’s NAND flash business would increase Foxconn’s control of the parts it procures for Apple to assemble their phones. Apple, in return, ensures that it gets the best NAND flash for its products, forcing its competitors to stand in line.
But….According to reports in the Financial Times, even if Foxconn successfully partners with Apple, Japanese government officials could still block the sale because they have reservations about al bidders with factories in China. “The Japanese government, Toshiba and its partner Western Digital will likely do everything in their power to prevent any buyer that could potentially allow technology leakage to China and South Korea,” … “Partnering with Apple will not eliminate their concerns regarding Foxconn.” [link]
There are also reports that a consortium consisting of SK Hynix and several Japanese financial institutions reportedly has offered more than $9B for a majority stake in Toshiba memory chip business [link, link] This would make Hynix a major player in both DRAM and NAND and make them more of a threat to rival Samsung. It would also put even more of the worlds memory supply on the Korean peninsula.
Any of you looking for Yann Guillou at SEMI Europe will have your emails bounce back like mine did recently. Yann is now at Unity SC. Unity was formed last summer by combining Fogale Nanotech’s SEMICON division with Altatech [link]. Unity SC remains a subsidiary of Fogale Nanotech with headquarters in Grenoble FR. Their goal is to provide process control solutions for the semiconductor industry, with a focus on the advanced packaging and MEMS markets.
They claim to have the only complete solution for 3D TSV and FOWLP.
So, if you’re doing advanced packaging and/or MEMS and looking for measurement of thickness, CD, surface profiling, TTV, bow, warp, roughness, overlay or defect inspection take a look at their offerings.
Continuing our look at fan-out presentations at the recent IMAPS Device Packaging Conference…
JCET (STATS ChipPAC)
As we detailed in IFTLE 331, Yole Developpement reports that JCET leads all FOWLP vendors edging out TSMC with a 37% market share. [link]
At the recent IMAPS Device Packaging Conference JCET discussed advanced 3D eWLBB-SiP technology.
He following slide is a nice summary of target applications for SiP packages.
JCET claims their ability to create ultrafine L/S ground rules, down to 2/2 in a 3 RDL layer format, enables improved routability and tighter component placement. In addition since eWLB eliminates the use of substrate, it reduces the overall package thickness by up to 50% (down to 0.2mm in 2017).
Through additional technologies like thick Cu RDL, embedded inductors and IPD integration JCET provides options to meet RF performance requirements of L, Q factor etc.
For all the latest in advanced packaging, stay linked to IFTLE…