By Dr. Phil Garrou, Contributing Editor
Before we continue our look at the recent ASE Tech forum, a word about the solar eclipse. Much of the media portrayed this as a “once in a lifetime” event. I clearly recall one in the spring of 1970. I was in my last semester at NC State, living off campus and it was mid afternoon. It stared to get dark, the winds stirred up and the animals (birds and dogs) became silent. The temperature dropped what felt like 25 degrees and then it began to reverse.
The event was memorable enough for Carly Simon to insert lyrics about the “elite cool people traveling to be seen at a solar eclipse” into her generational song “You’re so Vain” (1972). Actually, she was watching it a few miles from me with boyfriend/future husband James Taylor who lived in Chapel Hill NC where his father was a University Dean. Anyway, it was certainly an unusual natural occurrence and the 8/21/2017 total eclipsed was my second and probably last chance to see one.
For those of you that were in its path…hope you enjoyed it this time around!
ASE Tech Forum continued
Back at the ASE tech forum in Nijmegen, Bradford Factor gave an update presentation on FC, WLP and FOWLP. On one of his early slides, Factor states that ASE began their bumping / FC work in 2000. I will add to that, noting that this all began for them after they licensed the FCT (Flip Chip Technologies) technology package ~ 2000. This was the dawn of wafer level technology, I was running the BCB business for Dow Chemical at the time and we were working with FCT to “bring up” licensees ASE, Amkor and SPIL during this time period. Taiwan had become the center of bumping and WLP. This new “wafer level” technology was destined to become the backbone of the advanced packaging for the next few decades.
Product families for fan in WLP (known as WLCSP at the time) are shown below.
The technology evolved from the FCT printed bump to the Unitive plated bump to today’s copper pillar bumps.
The latest ASE bump and WLP roadmaps are show below:
The following “industry node status” is an interesting slide in that it shows us ASE’s assessment of where the foundries are on the scaling roadmap.
ASE motivations for Fan out WLP:
- Package Size
– Fine line redistribution (RDL) layers – Low profile by encapsulated chip and component -Flexible integration by multi-chip and stacking chip
- Cost Effective
– No substrate – Panel (next generation) – High production yields (including with RDL substrate / chip last)
– Signal integrity & electrical performance, lower power consumption and better thermal ASE FO-WLP technology Roadmap and Package types follow.
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