By Dr. Phil Garrou, Contributing Editor
Hope all my readers in the USA had a great Thanksgiving. For those of you around the world, this holiday occurs in late November in the US when families get together for a 4-day weekend. I was with my two sons and my granddaughters Hannah and Madeline (who you have watched growing up ) in Houston and it was great to spend some time together. Younger son Christopher, who is a Chef in Maine, joined us and helped with the cooking activities.
Now let’s finish our look at the 2017 IMAPS Conference.
Under the DARPA/MTO SHIELD program Northrup Grumman led a team of GaTech, Sandia, Kilopass and RFID Global solutions have developed a supply chain traceability and authentication method to protect against counterfeit electronic parts. The solution consists of the incorporation of a 100 x 100 x 20um “chiplet” (they call dielet) fabricated in 14nm CMOS. Authenticity is verified using an Rf probe to energize and communicate with the chiplet. Putting the size of the chiplet into perspective, the pic below shows the chiplet on the head of Lincoln on the back of a penny.
The chiplets are manufactured using GlobalFoundries 14nm FinFet technology. The 300mm wafers are thinned and the 20um dicing streets result in ~ 4MM chiplets per wafer. Pick and place of these tiny chiplets is “challenging” but they have developed a technique to insert them into the host packages. Process flow is shown below:
Kyozuka of Shinko discussed the “Development of Thinner PoP Base Packages by Die Embedded and RDL Structure.”
PoP structures can achieve thinness by embedding a die (or dies) into a package thus achieing height reduction for devices like APS (application processors). Their “die embedded with RDL” structures are shown in the fig below with design specs.
The process flow is shown in the fig below.
The FC process is done by TCB (thermos-compression bonding) followed by capillary underfill . After die mounting the cover layer of laminate is vacuum laminated and vias are laser drilled to make connection between the substrate and the top RDL. Expected issues with warpage were controlled by controlling layer thicknesses and copper density on the layers.
Via formation included laser drilling, desmear, electroless and electrolytic copper plating. Vias were tested under condition B (-55 to 125◦C) with 75 and 100um visa passed such testing.
Bart Vereecke of IMEC discussed “Investigation of wafer level packaging schemes for 3D Rf interposer multi-chip module”. The fig below schematically shows the structure with a GaAs MMIC mounted on the silicon interposer. The interposer consists of two metal levels sandwiched around a MIM cap layer. A Cu/Ni/Sn seal ring is designed in for bonding Si cap layer. The interposer is made of high resistivity Si to minimize Rf losses.
They examined different wafer level packaging approaches for fabricating the interposer and populating them using either D2D or D2W bonding of the MMIC components followed by wafer level encapsulation. These are compared in the table below. All of the process flows appear to have issues.
Bob Roberts of Axus presentation “Technology transfer for MEMS and Adv Packaging” was a nicely written review of the use of CMP and the thinning of silicon wafers which I can recommend to those wanting a refresher on the technology.
For all the latest on Advanced Packaging, stay linked to IFTLE…