By Dr. Phil Garrou, Contributing Editor
This week, I am interrupting our look at the 2017 3D-ASIP conference to take a look at consolidation in the equipment industry and the recent issue of IMAPS Advancing Microelectronics magazine.
IFTLE has explained many times that a sure sign of industry segment maturity is when the 3 top players have a combined > 80% market share. The best examples of this currently are hard disk drives and DRAM memory.
The latest data on the equipment industry market shares points to this segment being very close [link] . Had the TEL/ AMAT merger gone through, the industry truly would have reached the definition of maturity. I would be looking for attempts at other combinations in this segment to be coming soon.
Chip Package Interaction
Urmi Ray, VP of Technology for STATS ChipPAC (JCET) has edited a special edition on the chip-package interaction, which is definitely worth a read [Advancing Microelectronics, Nov/Dec 2017, V44, No 6.][Link]
As most of you know, CPI is the interaction between the semiconductor package stresses and the semiconductor device. Package stresses are caused by thermal, mechanical and chemical mechanisms. CPI contributes to various failure modes during package assembly and field life. The emergence of both fan in and fan out wafer level packaging, while delivering unparalleled form factor and cost improvements by eliminating the package substrate, has resulted in loss of a buffer layer between the chip and PCB resulting in additional stresses being transmitted to the die surface during SMT assembly.
Zhao and co-workers at Qualcomm discussed the “Electrical Chip- Board Interaction (e-CBI) of Wafer Level Packaging Technology”.
The industry is clearly moving packaging technology toward WLP and Fan-Out WLP to reduce packaging cost and form factor. One of the key differences between Flip Chip CSP (FCCSP) and WLP/FOWLP is the absence of a package substrate in the latter packaging options. For e-CPI in FCCSP, the package substrate isolates the chip from the PCB. Without the package substrate, the silicon die in WLP/FOWLP directly interacts with the PCB board. The mediation of the board stresses by the packaging substrate is now gone and one must evaluate the risk of direct PCB stress on the chip, i.e. electrical chip-board interaction (e-CBI). For WLP and FOWLP, e-CBI can be significant.
For example, they point to the fact that visual inspection of FOWLP reveals dimple patterns on the backside of the parts after board level underfill which correlate with the patterns of BGA depopulation. In the absence of the mechanical support from BGA solder balls in the depopulated areas, the board level underfill shrinkage pulls the thin silicon die towards PCB. FEA models have verified this phenomenon and reproduced similar “dimples”. Since the silicon die bends toward PCB in the BGA depopulated regions, this infers that tensile stress is being created on active silicon surface.
Ivor Barber and co-workers discussed “14nm Chip Package Interaction Technology Development.”
With the implementation of extreme low K (ELK) porous dielectric materials (k < 2.5) into the back end of line (BEOL) to reduce the interconnect capacitance and cross-talk noise and enhance circuit performance, the lower mechanical strength of the ELK, along with increased die size, difference in effective coefficient of thermal expansion (CTE) between die and substrate, and the use of higher stiffness lead free solder increasingly contribute towards ELK layer cracking. Chip package interaction (CPI) became one of the critical reliability issues that needed to be addressed to avoid electrical or mechanical failure in products.
In order to evaluate CPI risk and reliability concerns from a technology point of view, they developed a CPI test vehicle (TV) which must include the same BEOL stacks, same ELK material, same BEOL process, same bump technology, same substrate technology, same assembly process for the production of the same Si node. In their 14nm CPI development, a 14nm TV with die size of 21×21 mm2 with 140um bump pitch of SnAg bump has been selected. 40×40 mm2 substrate has been used in our CPI technology qualification. JEDEC standard tests (Precon, UBHAST, TCJ, MSL, and HTS) were used as criteria for the CPI technology qualification.
ELK delamination / cracks called “white bumps” are encountered as rigid lead free bumps would transfer more stress to weak ELK layers causing ELK crack underneath the bump. Unlike bare silicon dies, thermal deformation of packaged dies can be directly coupled to Cu/low-k or ELK interconnects, inducing very high local stresses to drive fracture and delamination. ILD delamination is caused due to dicing defects like micro-cracks and poor adhesion or mechanical strength of low-k/ELK dielectric materials under the thermal load of the processes like flip-chip assembly process or thermal cycling tests.
In order to improve the CPI margin, studies have examined passivation thickness, polyimide thickness, under bump metallization, CTE of substrate, and FBEOL. Simulation and DOE have shown that by using thicker Aluminum terminal metal and two layers of passivation, the CPI risk reduced significantly. So foundries have now implemented this dual passivation layer with Al terminal metal to enhance CPI reliability.
Simulation has shown that ELK stress are reduced with reduced bump pitch.
The fracture toughness of low-k/ELK dielectrics vs SiO2, is substantially reduced and is significantly lower than that of Si. It is thus much easier to induce defects like micro-cracks during dicing. Those tiny cracks can develop and propagate into the active die area and cause failure under thermal-mechanical stress. One approach to prevent cracking at the die edge or die corner is to apply patterned metal structures called crack stop around the perimeter, especially reinforced at the die corners. They found that double wall crack stop was necessary for products with large die size to provide protection for the dicing defects.
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