By Dr. Phil Garrou, Contributing Editor
IZM Fraunhoffer TU Berlin and Osram
Tanja Braun of IZM Fraunhoffer discussed “Fan-out and Panel level technology for Advanced LED Packaging.”
The ongoing miniaturization in LED chip size and thickness down to 200 μm and below requires adapted chip handling and assembly. Innovative solutions are needed to electrically connect top and bottom contacts of the LED guaranteeing at the same time a sufficient overall thermal concept. Polymer based package solutions need to consider the aging/yellowing of the polymers on constant exposure to intense light. High volume and low cost solutions are required.
A blue LED with an area of 1×1 mm² and a thickness of 120 μm was chosen for package development. The LED has one contact pad on the topside and needs an additional electrical connection to the backside. The overall concept for the SMD compatible single LED package is shown below.
Package size was designed to 1.6×1.6 mm² allowing the integration of a through mold via (TMV) with 100 μm diameter routing the contact from the topside to the SMD compatible pads on the package backside. Package mold thickness is 300 μm resulting in a mold layer of 180 μm on the backside of the LED. The backside of the LED is connected by a blind via with a diameter of 250 μm. The process flow is shown below:
Compression molding is used for reconfigured wafer encapsulation. Recent developments now allow panel molding for sizes up to 600×600 mm². Compression molding evaluation within this study has been performed on 200 mm with a wafer level machine from TOWA and with a large area panel mold machine from APIC Yamada using a tooling with a cavity size of 457 x 305 mm². For the LED package development a liquid black epoxy molding compound (EMC) has been selected with a filler particle top cut of 25μm. Material with small maximum filler particle size has been chosen to allow laser through mold and blind via drilling with precise geometries and smooth via walls.
Die shifting is one of the key challenges during “Mold first” FOWLP. Due to the different thermo-mechanical properties of carrier, thermo-release tape and epoxy molding compound dies move such that the die position is shifted with respect to placement position after cooling down from compression molding. This effect is also influenced by the chemical shrinkage of the molding compound. Die shifting can be overcome by using a fast AOI (automated optical inspection) in combination with maskless processing for die connection and rewiring. This would give the opportunity to tolerate larger die misplacement by adapting the layout to the real die position.
Vias to the top side ad backside are shown below.
Cavaco of IMEC discussed heir results on “Hybrd Copper Dielectric Direct Bonding of 200mm CMOS Wafers with 5 Meta Layers…” where IMEC reports wafer level electrical data and reliability testing results for 200-mm wafer to wafer hybrid copper to dielectric aligned bonding on short loop wafers which consist of five backend of line (BEOL) metal levels using silicon carbon nitride (SiCN) as dielectric. The fabricated 200-mm wafer pairs are representative of a real CMOS device structure as they are processed with five metal levels per test wafer in a 130-nm copper BEOL CMOS technology.
In the wafer to wafer hybrid bonding process, two substrates are connected simultaneously by a copper to copper metal bonding and by an inter layer dielectric (ILD) oxide bonding. Some of the main issues inherent to the hybrid bonding process are: the profile of the copper pads after copper chemical-mechanical-planarization (CMP); the oxide erosion; the used surface treatment before bonding; the wafer to wafer bonding alignment accuracy; the contact integrity; the contact reliability; and manufacturing yield issues.
The full bonding sequence essentially comprises a wet clean module, a plasma module for surface activation and a bonding aligner module. A bonding accuracy below 1μm can be achieved by using dedicated alignment keys on both sides of the wafers. Bonding misalignment on the X direction was of the order of 0.7μm. Afterwards, the wafers were brought into proximity and dielectric bonding took place. Subsequently, copper to copper bonds are formed during a post-bonding anneal step.
SiCN was chosen as the dielectric layer(a) because SiCN is known to have a higher bonding strength when compared to SiOx, or SiN and (b) because SiCN can act as a barrier against metal diffusion into the dielectric, which can take place when using SiOx in a hybrid bonding process that comprises copper line patterns.
To confine the copper bonding pad dishing/protrusion to values below 10 nm, a strict process control of the CMP step is required on all wafers.
In this study, both HTS and TC reliability testing were performed at wafer level. More specifically, TC testing consisted of up to 1000 temperature cycles, of one hour each, from -40 °C to +125 °C. HTS testing consisted of storing the wafers, in a nitrogen environment, up to 1000 hours at +125 °C. Zero-yield loss observed at the end of both TC or HTS reliability testing.
Gao and co-workers from Xperi discussed their studies on the “Development of Hybrid Bond Interconenct Tech for D2W and D2D Applications”
We have discussed previously the acquisition by Xperi (Tessera) of Ziptronix and their DBI bonding process [see IFTLE 253, “China Inc Seeks to Acquire GF; Tessera Acquires Ziptronix; Tezzaron 8 layer 3DIC “ (link)]
This DBI (hybrid bonding) technology has been licensed and widely adopted by players in the CMOS imaging sensor industry such as Sony and Omnivision [see IFTLE 325, “ Omnivision takes Ziptronix License…” (link)]
To the best of my knowledge al of the CMOS image sensor work is being done on 200mm wafers , i.e W2W. Rumor has it that the process is much more difficult when trying to do D2W or D2D bonding. Attempting to resolve this issue and expand the use of the process in their applications, Xperi has undertaken a study of the D2W process looking to compare it to the more standard TCB (thermos compression bonding).
Obviously aiming at the stacked memory business, their test structures consisted of a host wafer designed to mimic the logic controller in a HBM stack. The fig below shows an illustration of four dies stacked on top of a host wafer. Daisy chain coverage includes hybrid bonding between the following interfaces: host die to die 1 bottom: die 1 top to die 2 bottom; die 2 top to die 3 bottom; and die 3 top to die 4 bottom. Currently, the stackable die does not have through-silicon vias (TSV). Consequently, electrical testing is limited to the die 1 bottom to host die interface. For next phase of development, TSV will be included to enable electrical testing of all interfaces.
It is desirable to maintain the RMS roughness of silicon oxide on the bonding surface below 0.5nm to facilitate high bond energy between the silicon oxide components of the hybrid bond. A similarly low surface roughness of copper is also desirable (although less critical) to further increase bond energy. In addition, it is desirable to have the Cu surface slightly recessed from the oxide surfaces.
The table below compares the total process time and throughput of a bonder for TCB and hybrid bonding. The hybrid bonding process requires very low contact force. It is essentially a P&P only process. It requires no temperature profile, no pressure control and no dispensing of additional material. On the Toray bonder, they demonstrated that 10s and 1s bonding dwell time shows the same bonding results. On the Datacon bonder, we have demonstrated bonding dwell time of 0.1s. With addition of 0.5s material handling time to each machine, the calculated throughput is 2400 unit per hour (UPH) on the Toray bonder and 6000 UPH on the Datacon bonder.
Compared to TCB, the hybrid bonding requires additional processes for die cleaning, activation and anneal. However, all these processes are carried out in batch and does not limit the throughput of the bonder.
Bonds with poor electrical contact appear to be the result of particulate contamination . Such contamination is considerable reduced in a class 100 clean room environment. Optical images of the die stack is shown below.
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