Insights From Leading Edge

IFTLE 389 Samsung 2μm L/S Panel Level Packaging Technology Revealed at ECTC

By Dr. Phil Garrou, Contributing Editor

This week and next, IFTLE will take a look at the key Samsung presentations from the recent ECTC meeting in San Diego.

As we have said many times on IFTLE, fine pitch solutions is certainly an area where the major foundries have a packaging advantage over the OSATS. The Samsung Packaging Development Team presented a paper entitled “Fan Out Panel Level Package with Fine Pitch Pattern” discussing the technical challenges of fine pitch processing on a panel level process.

Samsung Panel Level Processing

Panel level package (PLP) is being examined because it appears to be the most cost-effective technology due to its large working area. Compared with 300mm wafer size, about 3 times number of units can be accommodated in Panel of 500 X 400 mm size. SEMCO (Samsung Electro-Mechanics) has developed a platform for FOPLP as shown in the fig below.  RDL technology enables the IO’s from semiconductors fanned out through RDL to PCB, while organic PCB is introduced as core structure in Fan-out area.

Many concerns remain regarding commercialization of Panel Level Packages related to process capabilities and yields. The most emphasized ones concern warpage and the generation of fine features. As we know, Fan out can be done RDL last or RDL first. As requirements of finer patterns are needed, RDL first process is seriously considered because fine patterns can be easily obtained on relatively flat carriers compared with molded wafers or panels. Samsung points out that currently patterns of about 10/10 um line and space has been successfully formed in chip first Fan-out package and 5/5 um of pattern is expected to happen in advanced Fan-out package, while 2/2 um of pattern required for die to die interconnection in such applications as 2.5D interposer drive the consideration of an RDL first processes solution.

In this study Samsung attempted to fabricate 2/2 L/S on glass and PWB panels of 415mm x 510mm size. The CTE of organic carrier composed of resin with glass was 8 ppm/C and the thickness was 0.6mm. The CTE of the glass carrier was also 8ppm/C and the thickness was 1.1mm. The Fig below compares organic carriers and glass carriers with regard to the extent of panel warpage.

The warpage of the glass panels was less than a quarter that of organic carrier. In addition, during the assembly process of large die with fine pitch micro bumps (typically 55um pitch) also requires very flat condition to avoid warpage caused non-wets or shorts.

Samsung feels that the concern that 2/2 um patterning on panels will be difficult may be due to the observed panel warpage and flatness. As the pattern pitch is decreased, available depth of focus (DOF) during lithography must be reduced, which requires very flat conditions. As the pattern pitch is reduced below 2/2 um, available DOF is decreased below 10um and toward about 5um level even though it depends on exposure equipment. Therefore, large panel warpage or high waviness on surface to be exposed may cause poor capability or yield with fine pitch.

Using the glass panels the Samsung group was able to do photolith and produce 2/2um L/S as shown in the fig below. A PBO dielectric was used to create 2 layers of 2/2 interconnect with 6um vias connecting them.

So a rigid carrier with high thickness or stiffness seems to be needed because multi layers on organic carrier resulted in the failure in exposing equipment (stepper) due to the high panel warpage. In case of glass carrier, about 5mm warpage was observed on the panel.  Even in that condition, the stepper table could hold the panel effectively under vacuum and there was no problem related with focusing the panel surface.

Another consideration regarding multi-layered panel was whether the pattern below passivation may affect the flatness of the passivation layer surface which consequently affects the fine pattern on it (i.e. is he surface planarized enough so that CMP or some other form or planarization aren’t needed between each layer of interconnect) . In the cross-sectioned image of 2/2 um pattern on second passivation layer shown below you can see the dip in the central area, which contained no sub layer features. Further study is needed to determine how much is flatness degradation due to lack of global planarization will induce failure in 2/2um pattern above.

Samsung also presented an excellent discussion on known good substrates.  In case of chip last RDL first process, the dies must be bonded to known good RDL. Therefore electrical test of the RDL carrier is a very important issue. One has to deal with the small bump pad size of about 20 – 25um diameter and the extremely large number of bumps (about 200K). A major issue is the probing of the interconnect. It is difficult because the electrical probe cannot be contacted on both side of all signal lines, but some must be checked by contacting on only one side of the signal lines. To check by only one side contact and decide if there is open or short, the capacitance of line or pattern must be measured exactly. Feasibility tests were done for one side contacted electrical test. The intentionally opened lines are well distinguished from the good signal lines as the line opened at the farthest position is differed by about 40% of measured values.

This is technology obviously still in R&D, but it is the strongest set of data that IFTLE has seen showing the possibility of manufacturing high density interconnect on large panel format…It certainly showed Samsung flexing it’s technical muscle !

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